With the New Year rapidly approaching, engineering editorial types like me are often called on to summarize the technology developments of the past twelve months. Doing that at ChipCenter is easy. All you need do is surf your way back through our on-line archives.
Looking into the future is a bit tougher. There are no URLs to rely on, nor do I have the Web equivalent of Harry Potter's highly polished crystal ball on my desk.
Nonetheless, it's the time of year when ChipCenter's senior editors make their annual predictions. In my case as a test-and-measurement analyst, I look at product development and deployment with a focus on test equipment and measurement technologies. Those of you who read my column know that I also review sensors and products used for data acquisition and control, as well as some aspects of industrial automation.
So, what do I foresee in the shapes mysteriously drifting across my crystal sphere?
It's An Analog World
For starters, it's apparent that the world according to Mr. Boole is no longer simply comprised of ones and zeros. As faster semiconductors proliferate, analog constraints such as ringing edges, transmission-line effects, and impedance matching are challenging digital designers.
At the same time, packetized interface schemes and communications fabrics such as HyperTransport, InfiniBand, RapidIO, and PCI Express are posing challenges of their own. Fewer tests are being made on parallel buses—assuming they're even available for probing in the first place.
Multiple processor/DSP designs, millivolt-level differential signaling schemes, embedded clocks, and systems-on-a-chip (SoCs) are fueling more complex and much faster products than ever before. Increased speeds and reduced margins spell less headroom for error. SoCs are increasingly difficult to test.
For some EEs, this complexity means embracing design-validation techniques. In the world of HDL-derived silicon, the pressure is on for better simulation as well as device, interconnect, and prototype characterization.
Many earlier generation EDA tools are no longer up to the task of making accurate predictions. Up-to-date modeling and debugging tools are needed. In the test domain, higher performance designs demand more built-in self test, more accurate instrumentation, better probing techniques, and new test approaches that can help ensure signal integrity and make measurements to confirm it.
In both manual and automated test, there's a need for better ways to trigger on high-speed signals in order to zero in on data of interest. If you can't pinpoint the source of a fault, a design—especially one based on an SoC—can be doomed to failure.
One trick will be to really verify that a multi-million gate IC, replete with embedded intellectual property and multiple cores, will work as it is intended to under any and all conditions. Increasingly, formal verification tools will be needed to ensure functional robustness and testability. The goal will be to detect defects in both design and manufacture. If you can reach those goals, you will be set for the next steps.
Moving Into 2003
What will those be? The images in my piezo sphere foretell two things. First, a unified Web-connected environment based on Microsoft's .NET initiative will influence instrument programming and applications development, targeting ATE and even bench-level test equipment.
What's cool about .NET is that you won't have to learn all the gory details of the Internet Protocol's TCP scheme to open and use remote "sockets," and you'll be able to interact with distributed test databases without the knowledge of a programmer. Developing and driving test equipment, and sharing the results across an enterprise's many departments—from virtually anywhere—will soon be as common as the holes in Swiss cheese.
Getting Down to Nano-Business
Second, my crystal ball says that today's ICs will soon be married to micro-electro-mechanical systems (MEMS) and nano-scale mechanical structures. Get ready for nano-science, nano-chips, nano-manufacturing, and yes, nano-business.
While my crystal ball doesn't reflect an earth-shattering nano-technology paradigm shift in 2003, it predicts that many of you will eventually be charged with designing and testing nano-devices. These devices will marry processor cores, parallel and serial buses, and memory, as well as chip-scale interconnects, sensors, and moving-part MEMS. The goal will be to manage these ponderously small structures to ensure defect-free designs and manufacturability.
For engineering organizations that embrace Web-based development tools in 2003, the doors of opportunity will open earlier. Nano-technologies may be just a bit further down the road, but not too far out there. In either case, my spherical prognostication machine shows that opportunity will knock on the doors of those design teams and enterprises with a vision for .NET and MEMs.
I'll leave you with those thoughts. It's time to fill my glass with some holiday cheer. Happy holidays and all the best in 2003!
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Eonic Solutions' Chairman and Marketing Director Eric Verhulst offers his observations on ASICs/SoCs in a Letter to the Editor he wrote in response to ChipCenter Senior Technology Editor Alex Mendelsohn's year-end observations through a techno crystal ball.
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