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Characterizing Interconnects Using Time Domain Reflectometry (Part 1 of 3)

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Accurate Prediction Required
TDR Scope Basics
The Impedance Peeling Algorithm
Computation of the True Z-Profile
Part 2: The Single-Line Modeling Approach

In this first part of a multi-part ChipCenter series, we look at time domain reflectometry measurement as a handy technique for determining impedance profiles of traces on circuit boards.

by Dr. Steven D. Corey, Principal R&D Engineer, and Dima Smolyansky, Product Marketing and Applications Engineer, TDA Systems Inc., Bldg 2, Suite 300, 4000 Kruse Way Place, Lake Oswego, OR 97035. Phone: (503) 246-2272. FAX: (503) 246-2282. Web: http://www.tdasystems.com.

As the performance requirements for computer and communications systems grow, the demand for high-speed printed circuit boards (PCBs) increases. It's not unusual to find that speeds as fast as 1 Gbit/second need to be supported by standard PCB technologies. The rise times of these signals can be as fast as 100 ps.

At these speeds, interconnections on PCBs behave as distributed elements, or transmission lines, and reflections due to impedance mismatching is a typical signal integrity problem. Vias between layers and connectors on a board create discontinuities that distort signals further.

Accurate Prediction Required
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To accurately predict the propagation of signals on a board, you need to determine the impedance of the traces on different layers and then extract models for board discontinuities. Time domain reflectometry (TDR) measurements have always been the measurement approach of choice for this type of characterization work.

Based on TDR measurements, a circuit board designer can determine characteristic impedances of board traces, compute accurate models for board components, and predict board performance more accurately. Let's look at how to get the PCB trace impedance profiles you'll need.

TDR Scope Basics
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In a simple TDR setup incident waveform amplitude at the device under test (DUT) is typically half the original stimulus amplitude V at the TDR source. The smaller DUT incident waveform amplitude is due to the resistive divider effect between the 50-ohm resistance of the source and 50-ohm impedance of the coaxial cables connecting the TDR sampling head and the DUT.

In this typical TDR oscilloscope equivalent circuit, two electrical lengths of the cable interconnecting the DUT to the TDR scope delay the waveform reflected from the load. The waveform is superposed with the incident waveform at the TDR sampling head.

The impedance of the board trace can be determined from the waveform measured by the TDR oscilloscope, V measured, which is the superposition of the incident waveform at the DUT and the reflected one, offset by two electrical lengths of the cable interconnecting the oscilloscope TDR sampling head to the DUT. Conventionally, the impedance of the board is computed from TDR measurements using an equation that relates the DUT impedance to the impedance of the cable interconnecting the TDR oscilloscope sampling head to the DUT:

Eq. 1

where _ is the reflection coefficient, which is a ratio of reflected and incident energy at the DUT:

Eq. 2

The reflection coefficient can be computed and displayed by a TDR oscilloscope. The equation (1) can be rewritten in terms of incident and reflected waveforms, or can include the waveform actually measured at the input of the oscilloscope TDR sampling head:

Eq. 3

Either equation (1) or (3) can be used to compute the impedance of the DUT.

The Impedance Peeling Algorithm
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For a simple DUT, such as a test coupon on a PCB, the equations above work quite well. However, in real life, a board designer has to deal with more complex structures, such as board traces that jump between layers, interconnected by vias within a board and connectors between different boards (for example, at a backplane to a daughterboard interface). Traces on different board layers can have different impedances, and vias and connectors constitute inductive and capacitive discontinuities that distort the signal propagating through a board.

Such complex structures result in multiple reflections occurring in the system at each impedance discontinuity. The resulting superposition of real and multiple "ghost" reflections in the system makes it difficult, if not impossible, to apply equations (1) or (3) directly. The lattice diagram in the figure illustrates the multiple-reflection effects.

This lattice diagram shows a TDR waveform propagating through a complex DUT with multiple impedance discontinuities. The superposition of primary reflections at each layer, and multiple secondary or "ghost" reflections between layers, makes it difficult to determine the impedance of each layer in the DUT.

Even for a simple test coupon, an SMA connector that serves as an interface to the board trace can create a situation where superposition of multiple reflections results in insufficient accuracy in determination of the coupon impedance.

Computation of the True Z-Profile
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The true impedance profile can be computed, however, from the TDR profile measured with a TDR oscilloscope using an impedance-peeling algorithm. It's also known as an inverse scattering algorithm.

From the lattice diagram, it's clear that Equation (1) can be applied to the reflection at the interface between Z₀ and Z₁ in order to compute the impedance of Layer 1:

Eq. 4

where the subscript 01 refers to reflection at the impedance discontinuity between layers 0 and 1. The reflected waveform at time t₀ is defined by the reflection between layers 1 and 2 and but also by the reflection and transmission between layers 0 and 1. The reflected waveform amplitude at time t₀ can be computed as:

Eq. 5

where t₀₁ is the transmission coefficient at the interface between layers 0 and 1, defined as t₀₁ + r₀₁. From this equation, r₁₂ can be determined unambiguously, and the impedance at layer 2 can then be found using Equation (1) above.

Eq. 6

This computational procedure can be applied to the measured waveform, consequently peeling layers of impedance. As a result, impedance at each layer can be computed to form the true impedance profile of the DUT.

In the next part of this multi-part ChipCenter feature article series, we'll explore single-line modeling and show how you can obtain direct readouts of impedance values for all sections of a board trace under test.

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