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Characterizing Interconnects Using Time Domain Reflectometry: Determining the Simplest Model for the DUT (Part 3 of 3)

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Less Than Normal Conditions
Good But Not Perfect
A Bibliography
Acknowledgements

In this third and final installment of our multi-part ChipCenter series, we look more closely at ways to determine the simplest model for the device under test.

by Dr. Steven D. Corey, Principal R&D Engineer, and Dima Smolyansky, Product Marketing and Applications Engineer, TDA Systems Inc., Bldg 2, Suite 300, 4000 Kruse Way Place, Lake Oswego, OR 97035. Phone: (503) 246-2272. FAX: (503) 246-2282. Web: http://www.tdasystems.com.

When you're doing printed circuit board (PCB) interconnect modeling, it's important to keep in mind that you need to determine a model for a board trace discontinuity that's no more complex than is necessary to represent the DUT accurately at a given system risetime or analog bandwidth. Let's examine the relationship between the risetime of the TDR oscilloscopes to the risetime of a DUT.

Typical TDR system risetime is quite fast, on the order of 30 ps to 40 ps. On the other hand, even today, in the world of superfast signals on current circuit boards, typical risetimes rarely reach 100 ps. More often they're on the order of 1 ns to 500 ps.

Less Than Normal Conditions
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With faster TDR system risetimes, DUT traces may exhibit losses that aren't present under normal operating conditions for the DUT. In addition, the impedance that the lumped discontinuities present to test signals is dependent to the highest frequency present in the test signal bandwidth, as described by equation (8) here:

The risetime versus analog bandwidth relationship for step-like TDR incident waveform--as it's implemented in TDR oscilloscopes--can be evaluated using equation (9), shown here:

For faster risetime, capacitive discontinuity will present a deeper "dip," but an inductive discontinuity will present a larger "spike" in relation to the impedance of the transmission lines surrounding the discontinuity. Consequently, the impedance discontinuity DZ in the DUT will be larger for a faster risetime. That may not accurately represent the impedance value at the DUT operating risetime.

Good But Not Perfect
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At the typical TDR oscilloscope risetime of about 35 ps, the correlation between the measurement and simulation of the given model is good, but not perfect. That's shown in the following figure. Note that the model represents the board trace with acceptable correlation, however, including connector discontinuity.

Here's a comparison of a simulated and a measured waveform for the DUT. In addition to the board trace, the SMA connector at the DUT interface is modeled. The model represents the board trace with acceptable correlation, including connector discontinuity.

However, once both waveforms are filtered to about 150 ps equivalent risetime, the discrepancies between the model simulations and measurements become negligible. The resulting model will represent the DUT with a high level of accuracy to the risetime of 150 ps, as illustrated in this figure.

This comparison of simulated and measured waveforms at 150 ps risetime shows that the correlation has been improved significantly at the user-defined risetime. There's no need for further refining of the extracted model.

You can conclude that using risetime filtering to verify the PCB trace model at the realistic device risetime will permit you to characterize the DUT with a model that's simple, but adequate to represent the DUT accurately.

You now have a general methodology for modeling PCB interconnects from TDR measurements. From the data acquired with a TDR oscilloscope, with the use of Iconnect interconnect modeling software, a circuit board designer can compute a true impedance profile for a PCB trace and accurately determine the impedance and propagation delay for a board trace running through several layers on the board.

The models for lumped discontinuities, such as vias and connectors, can be computed as well, and the overall model can be verified at the user-defined risetime, using a built-in interface to a SPICE simulator.

Accurate models for PCB components can be obtained quickly, resulting in lowered design costs and faster product time-to-market.

A Bibliography
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[1] M.D. Tilden, "Measuring Controlled-Impedance Boards with TDR," Printed Circuit Fabrication, February 1992.

[2] "TDR Theory", Hewlett-Packard Application Note 1304-2, November 1998.

[3] J.M. Jong, B. Janko, V.K. Tripathi, "Time-Domain Characterization and Circuit Modeling of a Multilayer Ceramic Package," IEEE Transactions on CPMT, Part B, Vol. 19, No. 1, February 1996, pp. 48-55.

[4] C.W. Hsue, T.W. Pan, "Reconstruction of Nonuniform Transmission Lines from Time-Domain Reflectometry," IEEE Transactions on Microwave Theory and Techniques, Vol. 45, No. 1, January 1997, pp. 32-38.

[5] J.M. Jong, B. Janko, V.K. Tripathi, "Equivalent Circuit Modeling of Interconnects from Time Domain Measurements," IEEE Transactions on CPMT, Vol. 16, No. 1, February 1993, pp.119-126.

[6] "TDR Tools in Modeling Interconnects and Packages," Tektronix Application Note, 1993.

Acknowledgements
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The authors thank John Rettig of Tektronix for his valuable comments and suggestions.

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