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Tough Test Traits Test Friendliness Pre-Synthesis Constant Vigilance About Jon Turino

As your functional design progresses, early--and constant--attention to designing-for-testability and built-in self-test can pay big dividends and hasten time-to-market.

By Jon Turino, Director of Business Development, SynTest Technologies, Inc., Sunnyvale, Calif.

Pressure to shorten time-to-market, coupled with increasing device complexity in system-on-a-chip (SOC) designs--as well as the need for ever higher product quality--compels us to turn our attention to design-for-testability (DFT) and built-in self-test (BIST). Unfortunately, DFT and BIST are often thought of as "back end" issues that don't need to be considered until the functionality of a new IC's design is cast in software and ready for placement, routing, and physical layout.

Look at the conceptual flow shown in the figure below. It reveals how many designs are subject to iterations caused by inadequate test coverage. The iterations shown in this diagram have a very negative impact on time-to-market.

This typical iterative design flow reflects late consideration of DFT and BIST issues.

Getting or developing high fault-coverage test vector sets in a reasonable period of time--whether from an automatic test pattern generation (ATPG) tool, or from hand development of functional vectors--requires that designs be inherently testable and include BIST where appropriate (such as with embedded memories). Finding out just how good the test vector set is usually requires running a fault simulation tool.

If the results from that tool show inadequate fault coverage, a tough decision must be made: Do you tape-out the design, knowing that it can't be tested adequately, or do you go back through a long, painful, time consuming iteration? This isn't a fun decision to make!

Tough Test Traits
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There are a lot of design characteristics that can make high fault-coverage test generation, regardless of the method used, very difficult. One example is Set and Reset lines that are tied "hard" to power or ground rails on sequential circuits. Another is free running, embedded, or gated clocks. These are often used in order to reduce dissipation. Long counter chains not configured as scan chains are another characteristic that can make high fault-coverage test generation tough.

The list can go on to over twenty DFT rules that must be at least considered as early in the design process as possible.

Test Friendliness
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The next figure shows a much more tester-friendly flow. While it may still be necessary to cycle through a design as it evolves, the work is all done at the front end--before logic synthesis and the rest of the steps from concept to production. This flow can dramatically reduce the impact on time-to-market, due to test concerns (when compared to the previous flow).

This design flow, with early DFT/BIST analysis and implementation, can dramatically shorten time-to-market.

What's more, BIST and boundary scan design (BSD) synthesis tools can be used to automatically generate test structures for cores, embedded memories, and logic. BIST and BSD can also be used for the overall SOC test controller and boundary-scan cells.

These structures should be designed in parallel with the functional circuit structure. That ensures minimum impact on things such as power, critical timing paths, and silicon overhead.

Register transfer level (RTL) code from test synthesis tools can be merged with Verilog or VHDL functional design code. The code can be fully analyzed for testability problems at the RTL level, prior to synthesis.

Pre-Synthesis
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Once that's been determined, pre-synthesis (ensuring that the design doesn't contain DFT rule violations) takes place. Then, to make the design really testable, full-, almost-full, or partial scan synthesis is performed. This has the effect of breaking any feedback loops in your design, structuring all of the sequential circuitry into an easily controllable scan chain (or set of scan chains).

It also drastically increases the controllability and observability of functional logic. Then, when the ATPG tool is run, high fault coverage, with the most compact set of test vectors, is almost guaranteed.

If it's necessary to use a partial scan approach due to circuit performance considerations, even the best ATPG tool may not be able to reach the level of fault coverage required to insure confidence that the final product can be tested to the required level of quality in the factory. In that case, it's necessary to add functional vectors to the vector set generated by the ATPG tool, and to grade the quality of those vectors with a fault simulator.

But, if the design has been made as testable as possible right from the earliest stages, adding the functional vectors is usually a manageable task. The chance of having to undergo a complete iteration, requiring a second set of logic synthesis, scan synthesis, ATPG, and fault simulation steps is minimized.

Constant Vigilance
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Early and constant attention to DFT and BIST as your functional design progresses can pay big dividends in reducing testing-related iterations that could hurt time-to-market. The next figure reflects a vertical DFT/BIST flow that operates in parallel with the functional circuit design. Beginning with Verilog or VHDL testability analysis to find any testability (and often synthesis) rule violations, tools can be used by your circuit design team to insert BIST for embedded memories, cores, and logic, as appropriate.

Full scan, or its subsets, can also be automatically inserted into the design following logic synthesis. Boundary scan, including I/O cell replacement, test access port RTL code generation, and a boundary scan description language (BSDL) file, can also be done automatically. That will typically give your team a savings of three to four weeks over manually performing those tasks.

Here's what a vertically integrated DFT/BIST strategy comprises. Using the right tools from product concept through design completion can make a big difference in the amount of time it takes to deal with testing, especially with complex designs.

About Jon Turino
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Author Jon Turino is Director of Marketing and Business Development for SynTest Technologies, Inc., Sunnyvale, Calif. Turino has also held senior management positions with Integrated Measurement Systems and Mentor Graphics, and is the author of three books and hundreds of papers on design-for-test and built-in self-test. He is also a frequent speaker at major design and test conferences worldwide, and has won numerous awards for his presentations. Turino also founded the IEEE P1149 testability bus standardization committee in 1986, and was instrumental in the adoption of JTAG boundary scan and the recently approved mixed-signal testability bus standards. You can reach Turino via e-mail at jon@syntest.com. You can visit his Web page at http://www.syntest.com.

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