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An Introduction to IEEE-1149.4 Analog and Mixed-Signal Boundary-Scan Test

Editor's Note: A PDF version of this article is available.

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It's No longer So Simple Enter Boundary-Scan Dot1 Principles: Electronic Probing The Register Structure Control of The Test Structure Mandatory Instructions Analog and Differential Pins Mixed-Signal Boards Dot4 Boundary Modules Achieving Control The Analog Test Bus More Capabilities Parametric Test Internal Test

This first in a series of eChips/ChipCenter articles on boundary-scan testing covers practical ideas to help you implement the IEEE's analog and mixed-signal spec. Following a brief history, author Wilkins provides guidelines for chip- and board-level implementation. This material originally appeared in a hardcover book published in 1999 by Kluwer Academic Publishers (Boston, Mass.) entitled "A Guide To The IEEE-1149.4 Test Standard" (ISBN 0-7923-9696-8), edited by Dr. Adam Osseiran, European Technical Manager at Fluence Technology Inc. The material is extracted from that publication with permission.

By Brian R. Wilkins, Department of Electronics and Computer Science, University of Southampton, Southampton, England.
E-mail: <brw@ecs.soton.ac.uk>

As we all know, circuits are commonly constructed using printed circuit assemblies. PCAs are substrates carrying a pattern of conductors (interconnects) on which separately manufactured components are mounted. Component pins make electrical contact with the interconnect.

In normal operation, a PCA typically connects to other parts of your system by way of separable contacts, such as edge-connectors. As we all know, this has been standard practice for constructing circuits for many years. The diagram here shows a typical printed circuit assembly with points of test.

Over the years, the testing of PCAs relied largely on the use of in-circuit testers, applying mechanical probes to individual component pins. This permits each component to be tested in isolation, by applying test signals to a component's inputs and monitoring test responses at the its outputs.

You can also test the interconnect this way by applying test signals to the output pins of driving components and monitoring responses at the input pins of driven components.

It's No longer So Simple
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Today, such procedures are increasingly difficult due to advances in technology. Components are more complex, and come in much smaller packages. The density of parts on boards has increased dramatically, while at the same time each individual component carries increased numbers of smaller (and in many cases inaccessible) pins.

Mechanical probing is becoming more difficult, and in some cases, such as with ball grid array (BGA) packages, impossible—unless additional probe pads are designed-in.

Enter Boundary-Scan
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This is where the boundary-scan standard comes in. Although its original intent was to make provision for chips and boards of all kinds, the difficulties posed by some particular circuit features (notably, but not exclusively, analog circuits) led to the task being sub-divided.

IEEE-Std. 1149.1, The Standard Test Access Port and Boundary-Scan Architecture, or dot1 (which had been brought to an advanced stage by the Joint Test Action Group, or JTAG) was taken forward to cope with purely digital circuits; analog and mixed-signal circuits were deferred for separate consideration.

The development of the IEEE-Std.1149.4 Mixed-Signal Test Bus (naturally referred to as dot4), began with a meeting of interested individuals in 1991. Back then, it was agreed there was a need for a test structure that could be used with mixed-signal ICs.

From the beginning, it was assumed that the new standard would be constructed as an extension of dot1, and would operate in harmony with dot1, while making provision for the testing needs of a wider range of circuits.

Because a dot4 chip is basically a dot1 chip with additions, and because the dot1 features and the overall control protocols are subject to the rules of dot1, it's essential, before starting to implement dot4, to become familiar with the provisions and workings of dot1.

So, let's briefly review the underlying principles of dot1, with attention to the limitations of dot1 when applied to practical mixed-signal circuit boards.

Dot1 Principles: Electronic Probing
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The basis of dot1 is that a boundary-scan cell is associated with every pin on a chip. Each boundary-scan cell contains at least one flip-flop, and these flip-flops can be reconfigured into a single shift register (dubbed a boundary-scan register).

The ends of a boundary scan register are brought out to dedicated pins on a chip. This is shown in the following diagram as TDI and TDO in an IEEE-1149.1 digital chip.

Two other dedicated pins (dubbed TMS and TCK) complete the Test Access Port. The TAP permits test equipment to gain access to every pin of every component on a board (assuming that every chip complies with dot1). It also lets you load and inspect data at the pins without needing to pass test signals through the chip. This is electronic probing, achieving test access without mechanical contact.

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