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Bringing Bit-Error-Rate Testing Up to Speed

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The Production Floor Isn't the Lab Systematic Problems Days Of Tests Not Needed Testing in Parallel Crosstalk And Glitches

Testing today's communication devices with a parallel bit-error rate tester can give comprehensive testing in less time, reducing bottlenecks in high-throughput operations. You also get to reliably identify bad devices.

By Bryan Lord, Product Marketing Engineer, Agilent Technologies, Colorado Springs, Colorado

In recent years, communication-network device speeds and performance requirements have risen to the point where measuring device quality is an ever-increasing challenge. Efforts to reduce power dissipation have lowered running voltages, reducing the voltage difference between a Logic 1 and a Logic 0, increasing the chance of error.

Today's device speeds routinely exceed 2.5 gigabits/second. As such, board and system manufacturers want assurances that devices will actually run reliably at that speed. Providing that confidence requires determining how often a transmitted or received bit is incorrect; you have to know its bit-error rate, or BER. The difficulty of determining BER depends at least in part on the test target, that is, the maximum BER that the component manufacturer will tolerate.

Conventional methods for determining BER include analyzing a so-called eye diagram, as shown in the figure below. To get an eye diagram, you generate a voltage-versus-time plot of a repetitive waveform on an analog or digital-storage oscilloscope.

The open area within the eye represents—at least qualitatively—the error-free region of the signal.

A comprehensive device test consists of applying a pseudo-random bit sequence, or PRBS, to the device, then matching device response to that sequence at enough points within the eye to determine its dimensions. (A PRBS is an algorithmically deterministic—and therefore completely predictable—bit sequence that nevertheless has the same statistical characteristics as a truly random sequence).

Theoretically, measurement points closer to the center will yield the lowest BER, while BERs in the vicinity of the traces will be much higher. The minimum acceptable area of the eye depends on the device's maximum BER specification.

The Production Floor Isn't the Lab
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For a designer examining a device on a lab bench, the goal is to completely characterize its behavior, including its idiosyncrasies. Lab tests include measurements of voltage output, current, jitter, pin-to-pin skew, setup-and-hold times, input sensitivities, and other digital parameters, as well as BER. The task in this case is to determine with high confidence that the device will function as the designers intended, and that the manufacturing process implements that design correctly.

Measurement requires running every conceivable combination in a long PRBS pattern (up to 2³¹-1 bits for gigahertz frequencies), perhaps 1,000 times. Each detector bit received is exclusive-ORed with a corresponding bit from the algorithmically generated known-good pattern or from a memory-based user-defined pattern. Any difference between the two will produce a 1 output, indicating a bad part.

If the device fails, the sequence of 1s may indicate the source or cause of the failure. A single 1 or one that occurs at random intervals is merely a random failure. Engineering such a failure out of the device, either at the device or at the process level, is extremely difficult.

Systematic Problems
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On the other hand, a pattern of 1s, such as a mismatch regularly every n bits, indicates some kind of systematic problem. Similarly, at the BERs commonly achieved on today's devices, the likelihood of two or more failures in a row (often called an error burst) is extremely remote. Therefore any such occurrence indicates a systematic problem as well.

Systematic failures are caused by specific conditions or situations in the design, in the process, or on the device itself. Further investigation often indicates a corrective action that will minimize or prevent the occurrence of that failure in the future.

Since designers working in the lab perform their characterization on one or at most a few devices at a time, test times and level of automation are essentially irrelevant. Common BER specs can range from 10^-6 to 10^-14 (that is, one error in 10⁶ to 10¹⁴ bits).

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