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Boundary-Scan Testing
Part 1: An Introduction

by Dr. R.G. "Ben" Bennetts,
DFT Consultant to ASSET InterTech, Inc.,
Richardson, Texas 75080-2718
Phone: (888) 694-6250
FAX: (972) 437-2826
www.asset-intertech.com Page 1 of 2

Jump to...

New Technologies to the Rescue
Why Boundary-Scan?
The JTAG Approach
A Closer Look
The Spec's Instructions
Optional Public Instructions
Built-In Self Test
Assembling a Test Flow
Generating Test Patterns
Diagnosing Defects
To Probe Further

Physical access to test points and nodes has literally disappeared in today's multi-layer circuit boards, but boundary-scan testability techniques can assure test coverage. But, you've got to adopt a design-for-test methodology.

More than ever before, board-level designers are finding that without careful planning during the design phase, a packaged board may be untestable once it reaches assembly and manufacturing.

Board designs have become so dense and so complex that sufficient test coverage must be designed into the product. If it is not, in all likelihood, test coverage will never be achieved. As a result, more engineers are paying attention to design-for-test (DFT) early in the design phase. It's fair to say that DFT is now a design imperative.

New Technologies to the Rescue
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Fortunately, while electronic assemblies and printed-circuit boards are increasingly difficult to test, new test technologies such as boundary-scan have emerged to overcome the difficulties.

Let's take a closer look at basic boundary-scan DFT principles. We'll begin our tutorial by examining the work of IEEE-1149.1, also known as JTAG (Joint Test Action Group). Later, we'll explore and explain DFT principles as they relate to boundary-scan at the chip, board, and backplane levels.

The most common board-level test protocol conforms to the IEEE-1149.1 JTAG standard, defined in the mid-1980s. IEEE-1149.1 provides for vendor-supplied or EDA-generated test models.

Why Boundary-Scan?
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Life was simpler in the electronics industry in the 1970s, wasn't it? Most printed-circuit assemblies (I'll call them PCAs) had only one layer and were built with through-hole assembly techniques. Testing could be done with automatic test equipment (ATE) and an appropriate bed-of-nails fixture.

Test access points were typically built into those boards. Probes from a bed-of-nails fixture could make contact with the board's test pads, and tests could be run on a device or cluster of devices to locate interconnect defects such as opens or shorts.

But as electronic systems of the following decades became smaller, the real estate on PCAs became more precious. Several changes took place, changes that forever complicated the test process.

First, designers weren't satisfied with placing devices on just one side of a PCA. With surface-mount packaging, devices could be placed on both sides of a board. This made it difficult for a probe from a bed-of-nails fixture to hit a test access point.

At the same time, PCAs migrated toward multi-layer constructions in order to accommodate the many device interconnections typically needed. Multi-layer boards exacerbated the problem of access to test points because physical test probes couldn't penetrate several layers on a PCA to test an interconnection below the surface of a board.

Add the advent of fine-pitch and leadless packages such as ball-grid arrays (BGAs) and chip-scale packages (CSPs). Physical access for testing for manufacturing defects was quickly disappearing on BGA and CSP circuit boards.

The JTAG Approach
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As these trends became apparent, the JTAG council began developing a methodology that could be used to test the physical interconnections of digital semiconductors—without physical access by test probes. Eventually, this work became known as the IEEE-1149.1 Test Access Port and Boundary-Scan Standard, a comprehensive digital test scheme based on additional device logic and a four-wire test bus.

At the level of a semiconductor device, boundary-scan testing requires that each primary input and that each primary output signal be supplemented with a multi-purpose memory element called a boundary-scan cell (see Figure 1).

Figure 1 - Boundary-Scan Principle

The boundary-scan cells in a chip are configured as a parallel-in, parallel-out shift register. As test data are loaded into this shift register, they're placed into the boundary-scan output cells, then passed to other devices be means of the interconnects.

Next, the other device's boundary-scan input cells receive the data, and eventually the data are transferred off the devices entirely. A device's boundary-scan cells contribute nothing to the functionality of the device, nor do they interfere in any way with the functional operations of the chip.

Data can also be shifted around a device's boundary-scan shift register, starting with a dedicated device input pin called Test Data In (TDI), and ending at a dedicated boundary-scan output pin, or Test Data Out (TDO) pin.

Another dedicated pin (dubbed TCK) provides the test clock. The last of this set of mandatory boundary-scan pins, called the Test Mode Select (TMS) pin, accepts serial control signals.

When digital semiconductors with boundary-scan cells are placed on a PCA, the TDO of one device is connected to the TDI of the next one to form a boundary-scan chain or path (see Figure 2).

Figure 2 - Using the Boundary-Scan Path

In the example shown in Figure 2, an edge connector on the board has a TDI input line. It connects to the first device in the chain. The TDO pin from this first device is connected to the TDI pin on the second device. This is repeated for all of the devices on a particular path or chain.

The chain is eventually terminated at the board's TDO on the edge connector. The other boundary-scan signal lines (TCK and TMS) are connected in parallel to the TCK and TMS pins on each boundary-scan device on the board.

With this type of architecture on a PCA, a boundary-scan test system (such as Asset InterTech's ScanWorks) is able to treat the entire chain as a single register that provides access to all of a device's inputs and outputs. This register can be used to test the entire device's interconnects. (In boundary-scan, a device's outputs are sometimes called drivers or transmitters, and the inputs are known as sensors or receivers).

When a boundary-scan test is applied to a board, the boundary-scan chain is used to load stimulus values into the device's output cells. The test signals enter (in boundary-scan parlance they're shifted-in) by way of the TDI line on the edge connector. The stimulus is applied across each device's interconnects in what is called an update operation.

Responses are captured at the device's input cells. After traversing the entire chain, the response values reach the edge connector's TDO and leave the board in what is called a shift-out operation.

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