On a printed circuit board (PCB), adequate test coverage doesn't happen by
accident from one boundary-scan device to another, or from a boundary-scan device to a non-boundary-scan device. If you, as a
board designer, follow certain design-for-test (DFT) guidelines, then you should achieve an acceptable level of test coverage.
If test considerations aren't taken into account, a PCB's design phase may end up being extended significantly to accommodate
the revisions needed to ensure adequate test coverage.
To achieve high boundary-scan test coverage, the first (and obvious) step is to specify as many boundary-scan-compliant devices
as possible. More boundary-scan devices on board will lead to better interconnect fault coverage for boundary-scan and non-boundary-scan
devices.
Another effective practice is to always validate the accuracy of the boundary-scan description language (BSDL) file for each
boundary-scan device used. An inaccurate BSDL file can cause test engineers and technicians to waste valuable time trying to diagnose
a supposed board fault when an inaccurate BSDL file may be the cause of the problem.
Distributing Boundary-Scan Signals
Back to top
In general, any on-board boundary-scan chain must be thoughtfully designed to derive as much benefit from boundary-scan-based test
and in-system programming as possible. First, access to the boundary-scan Test Access Port (TAP) should be provided at the primary contact
point on the board such as an edge connector or a plug-and-socket connector.
Steps should also be taken to eliminate skew in the boundary-scan signals (TCK, TMS, TDI and TDO). If skew
is present in the boundary-scan network, the boundary-scan interconnect test may produce incorrect results.
To reduce noise from backplane signals and signal skew, boundary-scan buffer devices, which are compliant with the boundary-scan
specification (IEEE-1149.1), should be placed on board at the TAP board entry and exit points. Texas Instruments' (TI) Addressable Scan
Port, as well as its octal and Widebus devices, or National Semiconductor's SCAN bridge devices are suitable for buffering purposes.
The TCK and TMS signals should be treated as critical signals, ensuring that they're both properly balanced, that no skew
is present in either signal, and that they're correctly buffered with no inversion. In addition, these boundary-scan signals should be
terminated to avoid reflections. On the TCK line, a 68 W series resistor with 100 pF to ground should be
used.
Termination of the TMS and TDI lines should be done with a 1 kW to 10 kW
resistor to VDD. If the optional boundary-scan TRST (test reset) line is present, it should be pulled to ground with a
resistor in the range of 470 W to 1 kW. TRST should also be buffered every 12
devices or so on the boundary-scan chain.
To dampen any signal reflections, a 22 W to 33 W series resistor should be placed
on the TDO line between the last device on the boundary-scan chain and the board-level TDO exit point. The TDO line
should have a drive capability of at least 24 mA.
Non-Boundary-Scan Devices
Back to top
Even though not all semiconductor devices are compliant with the boundary-scan spec, the presence of non-boundary-scan devices on a board
need not prevent achievement of high test-coverage—if you follow certain guidelines.
First, the signal I/O pins of the non-boundary scan devices must be characterized. Because the algorithm that will generate the boundary-scan
interconnect test pattern has no awareness of the nature of the pins of the non-boundary-scan devices attached to the boundary-scan chain, you
must supply the characterization data for these devices. This information includes whether the pins connected to the oundary scan are inputs
(I), outputs (O), three-state outputs (OZ), or bidirectional (IO).
Now look at Figure 1 below. Note that devices U2 and U4 are non-boundary-scan devices. For the three-state and bidirectional pins on these
devices, you will have to know what logic value on which pins will control the status of the three-state and bidirectional pins so that, if
needed, these pins can be placed into a safe high-Z or input-mode state. This would eliminate bus conflict.
Figure 1 - Boundary-Scan to non-BS Interfaces
This information is known as constraint data because it's used to constrain the bidirectional pins so that they behave as inputs and not
outputs during boundary-scan interconnect tests. This can be accomplished by placing a constraint value on U2's O_Enab signal.
Other types of devices, such as series resistors and line drivers, have a logical characteristic known as transparency. In transparency,
the logic values on the inputs are passed to the outputs with no change. If the boundary-scan interconnect test pattern generator is able to
take advantage of this characteristic, then nets n7 and n8 in Figure 1 could be treated as one continuous net, and test patterns
could be driven across this net for improved test coverage.
Several steps can be taken to maximize test coverage for non-boundary-scan devices. First, if possible, boundary-scan registers, or the
primary connection to a board, should have access to the non-boundary-scan pins. ICT nails should be used as a last resort.
Second, make sure characteristic data are available, including the device's transparency properties, as well as the enabling pins and
control value for three-state and bidirectional pins.
Where feasible, direct access to key control signals on non-boundary-scan devices should be provided so that devices can be configured to
the correct state during testing. And, if direct control isn't possible, indirect control should be provided from an unused boundary-scan cell.
Last, any free-running clock or watchdog timers should be controllable indirectly by boundary-scan cells.
Handling TRST
Back to top
Although the TRST line is a boundary-scan device option, having a TRST line on board has certain advantages as long as the
TRST signals are handled correctly.
Without TRST, boundary-scan devices on the board must power up in their reset state (according to the rules of the IEEE-1149.1
standard), but a synchronous reset (TMS held high for five consecutive TCK cycles) can also be applied, just to be sure. With
TRST designed into boundary-scan devices, this can be avoided, but TRST must be laid out properly at the board level.
The IEEE-1149.1 boundary scan standard requires that TRST go to a high (Logic 1) state when the signal line is left open-circuit.
This is needed so that the device is tolerant to an open-circuit fault on the TRST pin on any boundary-scan device. But, if the master
TRST signal is left floating during normal operations, then the boundary-scan device can be powered up in an unsafe manner.
Next
>>
