As shown in Figure 5, each board has access to all of boundary scan's test capabilities, including scan-chain integrity testing, interconnect tests, RAM tests, and cluster tests.

Because every board in the system has its own local test intelligence, each board plugged into the passive backplane can be tested independently and concurrently. The connection between boards across the passive backplane can be tested, but each board's local test-bus controller must be synchronized.

The second method for passive backplane testing would involve just one test-bus controller located on one of the boards plugged into the backplane. This is shown in Figure 6.

As you can see, the controller could act as the master test controller for the system and conduct tests on each of the other boards in the backplane, one after another.

Motherboard-Daughtercard
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Another common system-level multi-board architecture is the motherboard-daughtercard architecture. Several chip vendors such as TI and National Semiconductor have secondary scan-path selector devices that can connect multiple scan paths on the same board. These devices can be used to test motherboards with daughtercards using boundary scan as shown in Figure 7.

Now consider a design where one of these secondary scan-path selector chips is placed on a motherboard in the primary boundary-scan chain. When a daughtercard isn't plugged into the motherboard, the scan-path selector device simply bypasses the daughtercard scan chain. But, if a daughtercard with an on-board boundary-scan chain is plugged into the motherboard, the scan-path selector device automatically incorporates the daughtercard's scan path into the motherboard's path, creating one continuous boundary-scan path from the motherboard to the daughtercard.

With one continuous scan path from motherboard to daughtercard, boundary-scan tests can be conducted that will not only verify the interconnection of devices on both boards, but also whether the daughtercard is properly seated in the motherboard connector.

Backplane Test Guidelines
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To enable boundary-scan test over a backplane, your system and the boards that comprise it must be designed with specific capabilities. Chief among these is the inclusion of a test-bus master device to coordinate and manage the boundary-scan tests.

As we discussed, several devices from IC suppliers can provide overall control for the data transfers that are required for tests over a backplane. These chips support all the necessary boundary-scan protocols. When configured in a system, test-bus masters typically interface a general-purpose microprocessor to the primary backplane test bus (refer back to Figure 2).

A Real-World Application
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Boundary scan was successfully applied recently in a design crafted at Lucent Technologies. As a supplier of wireless base stations, Lucent adopted boundary-scan techniques to test device interconnects on boards in one of its wireless systems. The technique was also used to test the interconnection of boards to the system backplane.

To achieve its test objectives, Lucent knew that testability would be an important consideration throughout the development of its system. Indeed, the result of Lucent's far-sightedness resulted in a wireless base station that could be readily tested at every stage in its product life, including development, manufacturing, and field service.

Members of Lucent's design team for this base station chose a multi-drop boundary-scan architecture at the system level. This is outlined in Figure 8. Each board in Lucent's system implemented the TI-derived Addressable Scan Port as the gateway device interfacing the board to the test bus on the backplane.

Individual devices on each board were enabled and disabled through three-state drivers on the boundary-scan TMS and TCK lines. The boundary-scan tests were sequenced so that PLDs (programmable logic devices) were tested first, followed by FPGAs (field-programmable gate arrays), then memory buffers, then the system microprocessor, and finally the board's DSP chips.

Key Partitioning
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Lucent's test designers partitioned sections of its system and the boards in the system so that each partition could be isolated and tested independently. The cumulative effect of testing all the partitions was a comprehensive system-level test. Boards were also designed with more complex devices located at or near the end of a boundary-scan chain in order to simplify design-verification and manufacturing diagnostics.

At the level of an individual board, this architecture supported a number of critical boundary-scan tests, too. These included scan-path integrity tests, interconnect tests, and cluster and memory tests. The approach also supported on-board programming for flash memories. At the level of the system, test-bus integrity tests could also be conducted, as well as backplane interconnect tests.

Conclusion
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Although the versatility of boundary scan has been apparent to some designers ever since the IEEE-1149.1 specification was first codified, what began as a board-level test structure has now extended downward into chip-level test. It has also extended itself upward to support system tests across a backplane. Boundary scan is also now a critical backbone technology for DSP emulation and on-board programming. It's plain that boundary-scan technology will certainly continue to play an important role for years to come.

About The Author

Adam Ley is Chief Technologist for Asset InterTech, a global provider of boundary-scan test systems and design-for-test (DFT) services.

This article concludes our four-part ChipCenter series on design-for-test considerations and boundary-scan test.---AMM

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