Back around 1990, boundary scan's (IEEE-1149.1/JTAG) humble beginning
signaled a way to test interconnections between one or more chips and on printed-circuit boards (PCBs). At that time the
importance of virtual access to on-board chips may not have been fully appreciated.
Since then, IEEE-1149.1 boundary scan and its derivatives have been pressed into service on a variety of fronts. These include
in-system configuration (also known as on-board programming), in-circuit emulation, mixed-signal test, on-chip debug, and re-use
of device built-in self-test (BIST).
System-Level Tests
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Now, another—and previously unforeseen—use for boundary scan has popped onto the scene, and it's increasing in
popularity as savvy system designers deploy boundary scan across backplanes to perform a variety of system-level tests.
Testing the interconnection of computer and I/O boards to a backplane is just as critical as verifying the integrity of
chip-to-board interconnections. Yes, system-level test-bus protocols have been suggested (such as the IEEE-1149.5 Module Test
and Maintenance Bus), but no single method has been universally accepted by the industry.
However, because of its extensive implementation in other areas of electronic test, and the ready availability of
boundary-scan components, boundary scan has become a candidate as a system-level backplane-based test methodology.
One Fell Swoop
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A system-level approach to boundary-scan test can not only be used to validate the connections of boards to a backplane,
but it can also be used to validate the interconnection of chips to boards, all in one fell swoop. Depending on the unique
characteristics of a particular system, boundary scan can be implemented in any of several ways to perform backplane and
PCB interconnect tests.
The simplest configuration for a backplane-based system-level deployment involves a ring-like structure with a test bus
master device, as shown in Figure 1 below. As you can see, the test bus master IC is responsible for distributing and
controlling the boundary-scan Test Mode Select (TMS) and Test Clock (TCK) signals to all the boards on the
backplane (two are shown).
Figure 1 - The Ring Configuration
Various IC vendors make ICs that can perform the role of the test bus master. Figure 2 shows a typical configuration.
Available devices include the embedded Test Bus Controller (eTBC) from Texas Instruments (TI), National Semiconductor's
Test Master, and Agere Systems's Boundary-Scan Master (BSM).
Figure 2 - A Typical IEEE-1149.1 Test Bus Master, or TBM
The ring architecture is constructed by connecting the boundary-scan Test Data Out (TDO) line from one board to the
Test Data In (TDI) signal line on the next.
With this type of ring configuration, boundary scan can verify whether each board is properly plugged into the backplane,
and whether the chips on each board are connected to the PCB. Unfortunately, if one of the boards is removed from the chassis,
or is unplugged from the backplane, or if an internal scan chain on one of the boards has a fault on it, the ring and the
boundary-scan chain is broken, and no tests can be conducted.
Moreover, since the boundary-scan TAP (Test Access Port) controller state must be synchronized across multiple boards, this
architecture isn't tolerant of skew on the boundary scan's TCK signal that can develop as it's distributed to each board along
the backplane.
A Shining Star
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An alternative to the ring architecture is a star configuration, as shown in Figure 3. In this star, independent TMS
lines are routed across the backplane to each of the boards in the chassis.
Figure 3 - The Star Configuration
This star architecture lets you test one board at a time. What's more, a fault on any one of the boundary-scan chains on any
of the individual boards will not derail the rest of the system-level test.
As such, the star configuration certainly permits system-level interconnect testing, but it does have some drawbacks.
Unfortunately, a separate TMS line for each board in a chassis can lead to a wide test bus across a backplane.
There is an alternative, and it's diagrammed in Figure 4 below. This third approach is made possible by including an addressable
boundary-scan gateway device on each board in a backplane. This scheme can be characterized as a multi-drop architecture.
Figure 4 - A Multi-Drop Test Architecture
The gateway device in our multi-drop architecture monitors the primary backplane test bus for its address. When it
recognizes its address, the gateway device connects the primary boundary-scan TAP signal lines on the system's backplane
to the boundary-scan lines on the board.
As you can see, the multi-drop architecture creates a master system test bus with just one TMS line. That permits the
interconnections between each board and a backplane to be tested in a similar way to our star and ring architectures. In
addition, system-level tests aren't disrupted if a board is removed from the backplane.
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