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Test Resource Partitioning for Concurrent Test
Part 1: Introduction

Concurrent test of functional blocks can significantly cut test times and cost of a system-on-a-chip (SoC), keeping the test time constant with integration. That can alleviate the impact of expensive state-of-the-art SoC test equipment. But, testers aren't always designed for concurrent testing of blocks. Resource partitioning is required for concurrent test execution of functional blocks. Let's look at what's required for a successful ATE (automatic test equipment) architecture.

by Klaus-Dieter Hilliges, Ajay Khoche, Dave Armstrong,
and Erik Volkerink,
Agilent Technologies,
P.O. Box 10395
Palo Alto, CA 94303
Phone: +1(650)752-5000
www.agilent.com

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Non-Scaling Test Cost An Alternative The Cost-of-Test Dilemma Test Time and Throughput The Capital Cost Low Utilization of ATE Resources Low Utilization of the DUT Solving the Dilemma A New Communication Scheme The Challenge

Driven by function, performance, dissipation, small form-factors, component availability, and cost, IC process technology is integrating ever more functional blocks into a single package. A functional block can be an embedded core or a system interface controller (such as a Universal Serial Bus controller). It can also be a design block that's shared in-house, or it may be some intellectual property (IP).

State-of-the-art systems-on-a-chip (SoCs) embed cores from various IP providers and integrate them in an architecture to provide function and performance. As an SoC developer (essentially an IP integrator), you need to ensure that each core you use can be tested—preferably by the test approach proposed by the core provider, which might be BIST (built-in self-test).

Evolving industry standards as proposed by the IEEE P1500 Embedded Core Test working group and the VSIA (Virtual Socket Interface Alliance) strive to enable this fragmented design chain and a new IP business model. SoC methodology now empowers us to continue the integrating trend, and it also controls the inherent time-to-market risk of complex, hierarchical designs.

Non-Scaling Test Cost
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Indeed, the manufacturing cost per transistor follows Moore's Law; hence the cost per IC is reduced, even as function and performance increase. Test costs, however, don't scale with Moore's Law, becoming a bigger factor in the total manufacturing cost of a chip.

An evolutionary approach to testing heterogeneous SoCs is the use of SoC testers with a wide set of resources dedicated to testing the various capabilities of a device under test (DUT). However, conventional ATE architectures, designed to test homogeneous ICs, are unable to cater simultaneously to varying test conditions and the nature of the functional blocks in heterogeneous SoCs.

As a result, the testing of each functional block is typically performed sequentially. This results in other functional blocks of the DUT idling for significant amounts of time. The same is true for corresponding DUT interfaces and your related ATE resources. All idle for significant amounts of time.

An Alternative
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There is an alternative. It's concurrent test. Let's look at some of the issues and answers, systematically analyzing the SoC cost-of-test dilemma while defining the concurrent test idea and its benefits.

We'll also explore the challenges for concurrent test in design and ATE architectures. Let's use a simplified example (a cell-phone design) to illustrate that the potential benefit of concurrent test can be of the order 50 percent.

The Cost-of-Test Dilemma
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When looking at a highly integrated SoC, some characteristics become immediately apparent. For starters, there are typically many embedded functional blocks of different kinds, such as processors and DSPs, memory, CODECs, and phase-locked loops. Also, there are usually many different interfaces; many such as memory interfaces, peripheral interfaces, mixed-signal I/O, and JTAG are standardized.

While designing SoCs by embedding various functional blocks provides a smooth integration flow, and can lower the overall IC manufacturing cost, it can create a cost-of-test dilemma. Two main aspects of this dilemma are throughput and capital costs. There are also aspects related to low utilization of ATE, DUT, and DUT interface resources. We'll touch on these shortly.

Test Time and Throughput
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Typically each embedded core type and each interface type in a hierarchical SoC design requires either a different test method, or at least a different test period. On today's ATE this leads to executing the tests for each block type sequentially, hence the test time of an SoC that integrates a set of functional blocks is (as a first-level approximation) the sum of the test times for each functional block by itself.

Because of this, the test time increases as more functional blocks are integrated on your SoC. The impact is especially high in the case of low yields, assuming that stop-on-fail execution is applicable.

Sequential execution can lead to a slow increase of overall test coverage throughout a test sequence, as each test fully covers a portion of the die before stepping to the next test. As such, even a very crude defect in a functional block may be detected only very late in your sequence of tests.

The Capital Cost
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The types of tests you need to support also determine the ATE configuration that's required to test your DUT. For example, your target ATE may have to offer digital pins with scan-test capabilities, and one or more memory test Algorithmic Pattern Generators (APGs) with bitmap memory.

It may also have to support digital source and capture memories, as well as analog digitizers and arbitrary waveform generators. Additional RF instrumentation will be needed if RF blocks are integrated.

While state-of-the-art SoC test systems support all these capabilities, their cost is significantly higher than a mixed-signal, RF, or memory tester alone (these may have been used to test the functions as standalone ICs prior to integrating them in an SoC). Moreover, sequencing tests into multiple test insertions often results in increased test cost because of multiple base-system costs for multiple dedicated ATE systems, and the duplicated indexing overhead.

Of course, multiple insertions can be effective if an insertion can benefit from a reduced-pin-count multi-site test. An example is redundancy-analysis testing of large embedded memories using a dedicated memory tester.

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