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Making a silk purse out of a sow's ear by Mike Timko, Analog Devices, Inc. The building blocks available on a typical IC fabrication process are really not very good in absolute terms. Key transistor parameters such as transconductance, input threshold voltage and output impedance vary by at least plus or minus 20% and are not as good as can be produced in discrete form. Compromises are made in the qualities of one type of component in order to get a wider range of devices. Some devices, such as lateral pnp transistors on older high-voltage processes, are marginal at best. On the face of it, it does not seem reasonable that this collection of parts could be used to do things like measure voltages to an accuracy of 16 parts per million (a 16-bit ADC) and, over the years, there have been industry pundits who have publicly proclaimed that such a feat would never be accomplished. In fact, these components have been used to create performance and functions that are impossible in discrete form. How is this possible? Lots of things go into making a high accuracy IC but the fundamental reason that IC s can be as good as they are is that all the parts are made at the same time, of the same stuff and are so closely linked that what happens to one part, happens to all. The elements are so close together that the doping levels in the silicon, the thicknesses of the oxides, and the degree of etching all match to a very high degree. What's more, when characteristics do vary, they often do so in a predictable way. Identical structures on an IC have identical characteristics. Much of an analog IC designer's effort is spent finding new ways of exploiting that fact. I may not know to within 20% what a given resistor's value will be, but I do know that the second resistor, right next to it, will be the same to a small fraction of a percent. In amplifiers, this fact leads not only to low offset voltages and low drift, but to high open-loop gain and excellent common-mode rejection. Of course, there is a limit to how well things match. The uniformity of dopants and oxide thicknesses is not perfect, and etch uniformity gets more important as process dimensions get smaller. More of the analog IC designer's effort, with the help of the layout engineer, is spent trying to make structures that are immune to all the secondary effects. There are a number of well known, and a few not-so-well known tricks to accomplish this. The Basics The first and most basic way to exploit matching is to make sure that one side of any differential circuit is identical to the other. If you want low offset voltage from your op amp, the input transistors, be they bipolar, MOS, JFET, or whatever, must be laid out identically. But what does identical mean? Many circuits are laid out with mirror symmetry across the chip's center line. Designers do this primarily to control thermal feedback from the output transistors to the input. The power-dissipating elements are placed on that center line so that they affect both sides of the input circuitry in the same way, and any thermal feedback is common-mode. In this case placing the active parts of the input symmetrically across the center line from one another does the trick. Unfortunately, mirroring a transistor can introduce electrical asymmetry if the transistors themselves are not symmetrical. IC processes put a great deal of emphasis on being small, and the size you can make things is largely tied to how well you can align the various layers. There will always be a significant degree of variability in element parameters due to misalignment of layers -- at least for the smallest devices available. What this means to the analog designer and the layout engineer is that the elements have to be insensitive to any normal misalignments. You need both mirror and translational symmetry for the key components. This concept is very basic and has been recognized (at least by the successful IC designers) since the very first IC op amps. But it works only to the extent that the components match. Current analog IC technology goes significantly beyond the raw match of transistors. When Things Go Wrong There are always limits to how well IC elements match and those limits are often the limiting factor to the performance of analog circuits. Even though they are made from the same stuff, that stuff does not get applied perfectly evenly so that even transistors that are close to one another may have offsets on the order of millivolts in the case of bipolars, or tens of millivolts in the case of MOS transistors. Here we can exploit another property of the elements on an IC: variations in element parameters tend to be linear versus distance within small groups of elements. Therefore, we can combine multiple elements in certain patterns to cancel first-order gradients. The simplest structure that rejects first-order or linear gradients is the cross-quad, four elements arranged in a square. Diagonally opposed elements are simply wired in parallel to produce two matched elements whose combined characteristics are the average of their components. I say "simply" although, in a single-layer-metal process, wiring a bipolar cross-quad is anything but simple. You want to end up with electrical symmetry so things like the resistance (i.e. length) of the emitter wires must also be matched. In high speed circuits, or anywhere dynamic behavior matters, capacitive coupling must be kept equal, further compounding the wiring problems.
The simple cross-quad is a very effective structure and can produce improvements in matching of an order of magnitude in some cases. The cross-quad is an important structure to think about. Try to imagine how gradients affect the device characteristics and when the beneficial effects would break down. If you put a serious source of heat unsymmetrically near a cross-quad, the thermal gradient will not be linear. Putting a cross-quad too near the edge of chip, where thermal gradients are discontinuous and die-bonding stress is greatest, can also cause problems that cross-quadding cannot fix. Matching more than 2 Things start to get more interesting when there are more elements that need to match. Take the example of a 12-bit DAC in which the five MSBs are made up of 32 capacitors. The front end of this DAC is "segmented" which means that each time the five-bit code is incremented one capacitor is added. The capacitors only need to match each other to one part in 256 or 0.4% which can be achieved with a common-centroid layout of 64 unit capacitors. Think about a checkerboard, with each pair of squares opposite one another across the center making up a DAC capacitor. If all the capacitors match to the above levels, the DNL (differential non-linearity) of the top bits will be less than half an LSB. However, the INL (integral non-linearity) will depend critically on the order that the capacitors are assigned to the DAC codes. (Specified INL is usually calculated as the greatest deviation from a linear interpolation of the first and last code transitions. INL at a given code is also the running sum of the DNLs of all the bits added up to that code.) The common centroid layout will take care of any linear gradient but such a large area is likely to have some systematic variation from linear. It makes sense to pick the caps in an order that jumps around the array so that errors from any one area are not accumulated but are mixed with those from other areas. Not observing this rule can lead to at least several unnecessary LSBs of INL. The particular pattern that works best will depend on the particular circuit. Gradients other than purely linear may arise due to thermal stress, die bonding, or edge effects. Note that errors from these three sources are likely to be symmetrical across the chip, and therefore, not linear. One way to pick an order is to assume a pattern, a parabola for example, and find the order that minimizes that pattern. (Hint: An exhaustive tree search of all the possibilities by a computer actually does not take as long as you might think.) In Summary The development of high accuracy analog integrated circuits has been many faceted. Laser trimming, digital auto-calibration, sigma-delta techniques and a lot of just plain clever circuit design have all contributed to achieving levels of accuracy, precision, speed and astonishingly low cost that are simply not possible in discrete form. In digital electronics, the size of the elements and, consequently, their speed has been the driving force in the amazing progress in speed, density and cost over the past 20 years. In the analog IC realm, it is the inherent matching, exploited to the fullest, that has led to the equally amazing performance of today's DACs, ADCs, op amps, and the whole range of functional blocks now available. MIKE TIMKO has been with Analog Devices for 25 years and is a Division Fellow in the Standard Linear Products Division. He received SM and SB degrees in Electrical Engineering from MIT in 1970. He has spent most of his time at Analog Devices as a design engineer and was the lead designer on such projects as the AD590 temperature transducer, the AD574 12-bit ADC and the AD677 16-bit ADC.
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