I was recently involved in a purely analog-design problem where even though the task seemed straightforward, state-of-the-art design tools were taxed to their limits. In the end, due to time constraints and at the customer's behest, a very conservative approach was taken. The design ended up being overkill: So much so, that for the second generation I decided to develop and try a totally new simulation methodology.

The problem at hand was line-driving for ADSL (Asymmetric Digital Subscriber Line). What is ADSL? It is one of the main contenders for delivery of high-bandwidth on-line services. ADSL proposes to deliver up to 6 M-bit/s over as much as 18,000 feet of ordinary twisted-pair telephony lines. It can also coexist with the regular telephone service. Even though ADSL is a predominantly digital system, the line interface remains a difficult analog design task. The system, as currently proposed, consists of 256 discrete, modulated channels, each about 4300 Hz wide, occupying a bandwidth of approximately 20 kHz to 1.1MHz. It is easy to see why the system is sometimes referred to as discrete multi-tone or DMT.

To put some numbers on the signal levels involved we can work from the spec of -40 dBm/Hz power drive on the line. This number comes from a complicated relationship between channel noise and bit-error-rate (BER). Each carrier then is (10log(4300)-40) dBm, or -3.67dBm. Remembering that we are working at a nominal line impedance of 100 Ohms the equivalent sine wave amplitude for each carrier is 0.293 V. The total power transmitted by 256 of these carriers is (10log(256)-3.67) dBm or 20.4 dBm, only 109.6 mW. This doesn't sound like much but let's go on. If 256 of these carriers are randomly summed the resulting waveform resembles Gaussian noise (Fig. 1). In fact, it is a psuedorandom noise signal. The average power might be fixed, but the peak voltage over a given time interval will have a probabilistic distribution with a maximum possible (all carriers in phase) of 75 V! Fortunately, the probability of this happening is infinitesimally small. In fact the peak-to-average ratio (PAR), or crest factor as it is commonly called, has an expected value of 3.2; at a value of 5.3 the probability is already only 1 in 107 . So if we limit ourselves to 5.3 as the maximum crest factor, we need approximately 35 V peak-to-peak drive capability on the 100 Ohm line. This still represents a lot of dynamic headroom in order to deliver only 109.6mW of average power.

The stochastic nature of the ADSL signal also poses some interesting problems if one wants to validate a design before actually manufacturing it. There is no simple stimulus -- like a few cycles of a sine wave or a voltage step -- that will guarantee to some level of confidence that a design will perform as required. An example here will show that using a SPICE transient analysis with a real ADSL signal, even though it is very computationally expensive, is possibly the only way to examine the performance of a given design before committing it to silicon.

The first problem was to generate a synthetic DMT waveform. I wanted to stay as close as possible to the actual ADSL system, so I chose to generate an 8x oversampled waveform (4096 points) of one symbol period (~223 micro-s). 256 equal-amplitude (0.293 V) carriers spaced at 4300 Hz were summed with a random phase relationship and sampled every 1/(4096*4300) s. All computations were done with double-precision math to avoid quantization errors.

Several carriers were left out (0-3, 16, 52, 122, 191, and 250). A customer with a large body of ADSL design experience suggested the selection of these numbers and I accepted them on faith as a good starting point. The results of the simulation will now produce the spectral contamination of the empty carriers by the intermodulations between all the other carriers. The performance goal is a maximum contamination of -65dB. As previously stated the crest factor of the resulting signal depends on the random phases of the carriers, and itself will be random with an expected value of 3.2. It was easy to generate waveforms with nearly that value but to get one with a value of 5.3 took more than 10,000 tries. Luckily, I only had to do it once. Figs. 1 and 2 show, respectively, the time domain and frequency domain representation of this 5.3 worst-case crest factor signal.

The second problem was to set up the simulation. From previous experience, I was convinced that a purely mathematical simulation was not going to give a complete picture of the situation. Amplifier nonlinearities are typically enclosed in a feedback loop and even the simplest examples of closed form solutions are intractable. I opted instead for a full top-level transient analysis using a 4096 point piecewise linear waveform generated from my data. This was a rude awakening: Even a single op amp (~100 transistors) took more than 48 hours to run through the entire waveform. The discontinuities in the waveform stimulate behavior on the sub-nanosecond level, and running the simulation for 223 microseconds. meant an enormous number of timepoints were needed for convergence. Problems like this are inherent in even state-of-the-art SPICE-like tools. This led me to try a hybrid-macromodel/real-device approach. The idea was to isolate amplifier non-idealities by modeling only part of the amplifier with real devices and use macromodel concepts for the rest. Of course, judgement must be used, as it would be easy to generate a physically-unreal amplifier. Since I have limited space here I can only present some of the results that one might achieve from working along these lines.

The power/performance trade-off is key to this application so I chose to explore the effects of output stage bias. The amount of class A/B bias in a voltage-out amplifier will have a strong effect at the crossover point between sourcing and sinking of current which will generate harmonic as well as intermodulation distortion. I simulated a differential voltage-out amplifier with only the output stages consisting of real devices. The supply rails were chosen so that even the high crest factor signal had 3.0 V of headroom. I tried several of my simulated ADSL signals and the results for each were very similar. Even thought the input waveform had a flat power spectrum the spectral contamination was noise-like with a large spread in values (>20dB).

Examining the results (Fig. 3) in the region just above 1.1 MHz one can see this effect. The worst case peak is just under -65 dB, while the bins that were left empty, for this particular test signal, only catch a -70 dB peak. It would not seem unreasonable then that some other valid test waveform would land a peak right on one of the empty bins. This observation leads to a very important conclusion: If this spectral noise floor could be characterized as a probability distribution, a single simulation could predict system performance. The idea here is that a statistical estimate could be made for the probability of one of the 256 bins of interest being contaminated by more than -65 dB. This knowledge, in conjunction with knowledge of the error-correction algorithm, could be used to guarantee an acceptable BER. To verify that designing for -65 dB THD on a full-scale 1.1-MHz sinewave was indeed overkill, I ran that simulation. The result (Fig. 4) shows that this simulated amplifier can only do -40 dB of THD even though it easily passes the high crest factor ADSL signal.

This is basically where I am right now, struggling with CAD tools trying to solve a very analog design problem in the midst of a mostly-digital system. When I started out in this business there was no CAD, but I have learned to embrace UNIX, C, PERL, etc. rather than shun them as some of the older-generation engineers have. I can't help but think sometimes that an old-fashioned analog simulator -- better known as a breadboard -- might have given these initial insights faster than my workstation. On the other hand tackling these kind of problems has helped me understand the limitations of computer vs. physical simulation and has made my workstation a useful tool in my day-to-day work.

Scott Wurcer joined Analog Devices, Inc. in 1974 after earning a BSEE from MIT. Working first as a product test engineer he moved to design in 1979. His designs include the AD524 family of instrumentation amplifiers, the AD711 family of op amps and, recently, the AD797 and AD815/816. He was appointed Division Fellow in 1996.