One of the questions that comes up perennially in the halls of Analog Devices, doubtlessly discussed often by our competitors, and certainly tossed around by the well-dined and -wined speakers in numerous conference panel sessions is this, "What is the future of the Big B?" -- the bipolar transistor -- held in parenthetical tension against the tacit observation, "Now that CMOS is here?"

Putting on my management hat, as briefly as possible, this is of course a question about investment strategy. The stakes are high. It is well-known that since the earliest days of electronics having access to key technologies is critical to the success of a microelectronics corporation; technologies which are, quite literally, its life-blood. It is impossible to manufacture competitive products without such access, and it is difficult to be a leader in the integrated circuit business without having at least some of these technologies in-house; they are often the most powerful distinguishing features of an IC producer. But when it comes to investment in bipolar -- now regarded by many as a technology on its way out -- how much is adequate, and how much is a luxury?

A modern, multi-faceted corporation such as Analog Devices must draw on a pyramid of technologies. At the base are those silicon technologies which have traditionally been our bread and butter, and which show signs of remaining in a firm position for some time to come: The generic junction-isolated bipolar processes. With these, we manufacture a wide range of standard linear and nonlinear signal-processing, generation and power-management products. In a layer above them are the fully-complementary bipolar (CB) processes, some still junction-isolated, the more powerful ones using dielectric isolation with silicon-on-insulator techniques. These technologies are enhanced by the use of perfect (ultra-linear, zero-TC) thin-film resistors (which are sometimes laser-trimmed), high-quality capacitors and, in some cases, inductors; these are used to fabricate advanced high-speed products, including many employed in modern high-performance communications systems.

Above these is a strata of several BiCMOS processes, which Analog Devices pioneered in the late seventies, the more recent of which combines a 25-GHz npn transistor with a 0.6-ým CMOS process; some provide a combination of complementary MOS and complementary bipolar (called CBCMOS). These versatile processes are aimed at getting the best of all possible worlds, with only moderate cost add-ons. It is interesting to note, however, that there are few compelling examples -- you can count them on the fingers of one hand -- in which a tight synergy between bipolar and MOS exists within a single circuit cell, where a unique function could not be realized in any other way.

Then, roughly in the middle of this modern pyramid, there is a broad and substantial body of CMOS, mostly provided by foundries, ranging from 0.8 ým down to 0.25 ým at this time. These are obviously the technologies of choice for all digital signal processing applications, which utilize immense numbers of transistors (one of our SHARC processors uses 29.8 million of them.) They are also widely used in DACs and ADCs, ranging from commodity products for multimedia, including digital video and audio, up to advanced high-speed high-resolution converters. They are widely regarded as the quintessential technologies of the future. The chief appeal of CMOS processes is generally reckoned to be their relatively low cost combined with extraordinarily packing densities and high yields. Further, these processes are widely sourced. Such primordial virtues, on top of the fact that CMOS digital circuits are very fast, outpacing earlier bipolar ECL logic speeds, guarantee that CMOS will be the main technology of importance to this industry for decades to come. The outlook for exotic alternatives such as quantum logic can only be described as "uncertain" . . .

At the pinnacle of our investment pyramid is a topping of gold-plated specialty processes, some of which are public knowledge, others not. One of those that is public is our capability to manufacture micro-machined devices of various kinds, many of a sensor variety, most notably accelerometers. The key to success in this field is being able to achieve high yields in components that have tiny moving parts with dimensions comparable to viruses, and combine them with signal-sensing and actuating elements. It is likely that this part of the business will flourish as the need for physical and chemical sensors with smart signal processing proliferates; there is a strong prospect, too, that micro-machined crosspoint switches and filter resonators will come into their own in the next few years. Also up there at the top are such things as GaAs and SiGe technologies, waiting their turn for a place in the sun. In all, Analog Devices has about 35 distinctly different semiconductor technologies to draw on, many having several variants, with the predominant revenue-generators having a bipolar content.

So, Who Needs It?

Thus, the question, "Whither bipolar?" is of more than academic interest to us, with such a large investment base. Having the benefit of a broad range of technologies, we can afford to take a balanced view but, not surprisingly, opinions differ. Most agree that as a logic technology it's a bit iffy these days but, ironically, not so much because the bipolar transistor is inherently ill-suited to logic. Part of the problem with bipolar logic used to be "power consumption." The style of CMOS logic based on an inverter topology (which is surely one of the wonders of the modern world) held out the nice prospect of a logic-gate current consumption that was extremely low, "Because the gate only conducts during logic-state transitions." This is certainly true in quartz watches, as well as in many other low-speed logic systems, and of course in memories. But, as anyone who's put a finger on a Pentium knows, CMOS is manifestly not a low-power technology when clocked at several hundred MHz, because those transitions occupy most of the cycle time. What's worse, using synchronous logic, the supply current comes along in amp-sized bytes, making power-bussing a problem of nightmarish proportions and the management of "ground bounce" a job for thick copper.

For this reason there has recently been a return of interest to differential-logic structures that look suspiciously like CMOS incarnations of the CML and ECL of olden times, using constant-current tail biases. The benefit of CMOS in logic is then not quite so clear from a performance point of view, and it could be argued that the lower logic swing needed in tightly-packed and locally-optimized bipolar cells is advantageous (about 5 kT/q, or 125 mV is plenty, when using a differential signal path) while, by contrast, CMOS swings in inverter-style logic are rail-to-rail, and in differential current-mode logic may be up to ten times higher than needed for bipolar. This underscores the "high-g_m" benefits of bipolar transistors. Some years ago, Analog Devices invested in a startup called Bipolar Integrated Technology (BIT) in Beaverton, Oregon, that had this particular bee in its bonnet; it was going to change the world with bipolar microprocessors. But it didn't, and the company was eventually disbanded. Why did it fail?

Part of the answer lies in the matter of yields: Even a non-epi bipolar transistor process, such as used by BIT, has a higher sensitivity to defects than a process using majority-carrier devices. And part of the answer lies in the matter of skill sets: There are fewer new designers who know anything about bipolar logic design. A further part of the answer is to be found in the lack of software -- design, simulation and layout tools -- that has been developed for bipolar VLSI and, consequently, the absence of libraries of high-level logic cells. Another reason is the practical matter that one can include CMOS memories having near-zero stand-by current into a micro-processor, DSP or other digital function. Probably the biggest reason for using CMOS, however, is that it is supported by an immense investment in fabrication equipment and global infrastructure, often with generous government subsidies, as in Taiwan. It is unquestionably the leading technology.

With the force of destiny on the side of CMOS for digital applications, it was not at all surprising that a few visionaries began to promote an interest, perhaps a couple of decades ago, in an idea that seemed at the time little short of preposterous, "What is to prevent us," they asked, "from using cheap, plentiful digital CMOS in pure analog processing and in analog-digital converter applications?" Bipolar aficionados such as myself smirked a little smirk, and sagely noted that "time will tell." We were to be sobered up by developments, starting with such things as switched-capacitor techniques, which use a radically different paradigm for signal-processing based on charge conservation, rather that the BJT approach to design based largely on currents in "dissipative" resistors. The proliferation of such solutions since then leaves little doubt that such is indeed not only possible but, in many cases, is preferable to a bipolar solution even -- maybe particularly -- in wireless RF/IF applications. And this is where the whole issue gets to be interesting.

The primary driving force behind the original work on analog design in CMOS was largely, I think it's correct to assert, because of its widespread availability and accessibility (not just to commercial designers, but -- and this is critically important -- to students), along with the prospect of low wafer cost and the inherent potential for mixed-signal implementations. Few students have had much of a chance, in recent years, to get their hands on a decent bipolar process, so they understandably are often ignorant about what can be done with "real transistors."

How About Cost?

As for wafer cost, though, that is highly moot since many analog chips are quite small. The full manufacturing cost for a CMOS part is about the same as that of its bipolar counterpart, by the time one has factored in the package, test time, the preparation of the supporting documentation -- including the data-sheet and the applications notes -- the overall cost of market research, engineering, sales and distribution: In short, it is the total cost of delivery for a moderate-volume standard product. It is my view that the "cost advantage" of CMOS for medium-scale analog products is invariably a red herring. And as for mixed-signal, more is said than done about such things. Several recent case histories show ambitious mixed-signal projects in RF communications systems being partitioned back down into smaller scales of integration in second-generation developments, for a variety of reasons.

On these grounds, then, bipolar remains competitive. For a company like Analog Devices, with such a strong product portfolio based on bipolar technologies, and many more new designs in development -- from dc power management to LF, IF, RF and microwave sub-systems-on-a-chip -- it would be rash to pull back on bipolar process development at a time when it is only apparently threatened by CMOS. The question that is interesting here is not really whether bipolar is an inherently strong technology, or even a "superior" one. Those kinds of comparisons are often more emotional than rational, reflecting one's experiences and preferences of style. The question that needs to be asked by analog designers is this, "Putting aside all the questions of destiny, accessibility, familiarity and cost, is it possible that CMOS may be able to do things that bipolar cannot, that is, might it actually offer a performance advantage?" There's the real heresy.

And the answer, I believe, is, "Absolutely!" Not in every application, as some CMOS evangelists teach, but in many that were formerly seen as the exclusive bailiwick of bipolar. It is ironic in the extreme that the very quality that makes the bipolar transistor so appealing, namely, its fundamental junction law behavior, in which current bears a precisely exponential relationship to an applied voltage, should also be its Achilles' Heel. To see the usefulness of an exponential relationship, one needs to first calculate the transconductance, g_m, as a function of collector current, I_C. It transpires, within the confines of a single line of algebra, that g_m is exactly proportional to I_C.

That alone is a powerful concept, opening the door to the literally hundreds of cell concepts that have been developed since the late 60's. But it's even better than that. The g_m is exactly equal to I_T/V_C, where V_T = kT/q, over seven or eight decades of current, independent of the size of the transistor, and even independent of the technology (for example, a silicon-germanium or even pure germanium device conforms to this basic law as accurately as a silicon transistor.) This marvelous and even slightly mystical behavior led me to coin the term "translinear", in 1975, to describe in a word the magic of bipolar devices: the transconductance is a linear function of collector current.

Nothing like this occurs in a CMOS transistor. Its V_DS-I_GS characteristics are a perverse potpourri of regions, from sub-threshold operation, where the optimistically-inclined say it's just like a bipolar transistor (it's not), through moderate inversion, where even recent professional papers like to assume a quadratic relationship (it hasn't been for years, but it makes the math easy), on up to strong inversion, where who knows what may happen to the algebra. Every combination of channel width and length is a special case. Most would agree that, at least in "saturated" operation (V_DS>V_GS), CMOS devices don't obey many laws that one could call useful. And even driven hard, the low values of g_m that can be attained are hard to live with.

Things are a bit more fundamental in the so-called linear or triode mode of operation, but not much. Surface states in the gate region make prediction of the threshold from one device to its neighbor something of a guessing game. And there's always the question of what is happening due to the back-gate bias. Even the hallowed assumptions that, "Well, at least the gate current is zero, and the source and drain currents must be identical" aren't quite true, particularly for deep-sub-micron devices. In short, compared to the mathematically pristine bipolar transistor, the CMOS device is a crock.

So, CMOS Is Useless?

But . . . but . . . not a broken vessel to cast away without first seeing what it could become. Or without being honest about the shortcomings of bipolar. For while those reliable translinear properties are very appealing from an analytical perspective, they hide a darker side. Summarized in short, the chief weaknesses of a bipolar are as follows:

• An exponential V-I law is the last thing you need in low-distortion amplifiers and low-intermodulation mixers. The strongly nonlinear relationship between I_C and V_BE requires the use of emitter degeneration elements (traditionally resistors, but inductors in LNAs) to "dilute" the nonlinearity. A quadratic law would be preferable, and in fact the more-nearly constant g_m of a sub-micron CMOS device versus channel current is highly advantageous in RF applications.
• The shot noise of a junction device sets a fundamental lower limit to the attainable noise figure in such applications; it generates 0.46 nV per root-Hertz of voltage noise spectral density across an emitter-base junction, at 27ýC, when I_C = 1mA, and decreases only with the square-root of I_C. Just as for the "good" properties like g_m the shot noise behavior of a bipolar transistor is quite independent of device size and the particulars of the technology. (Thus, SiGe is no better in this regard, or the previous item.) Majority-carrier devices have no shot noise and can, in principle, provide low noise figures at lower bias current than bipolar. CMOS is a majority-carrier device, but inferior to GaAs MESFETs in this particular respect.
• Bipolar transistors have a noise current associated with the base circuit. This current can best be modeled as the collector shot-noise, sqrt(2qI_C), divided by the ac beta which, it must be remembered, is approximately f₁/f_s, where f₁ is the frequency at which the magnitude of beta falls to unity, and f_s is the signal frequency. For example, with f_s = 2 GHz and f₁ = 20 GHz, the ac beta is only 10. Thus, any attempt to lower the overall noise by increasing I_C, as suggested above, must be tempered with the realization that eventually the degradation in SNR arising from base shot noise will become equal to that due to the emitter shot noise, and thereafter overtake it. CMOS transistors, by contrast, have insignificant gate noise under ordinary conditions of use, in common with GaAs MESFETs.

So the prospects for CMOS in RF applications appear to be very good, on the basis of fundamental considerations. On the other hand, there remain many significant obstacles to be overcome, not least of which is the notoriously low transconductance -- more accurately, the low g_m/C ratio -- of these devices. Some excellent work is being done in this field, notably by the students under Asad Abidi at UCLA and Michel Steyaert at Leuven, though at times the bold claims made about these experimental ICs being ready to replace, at a stroke, all of the components residing in the RF sections of a wireless hand-set, need to be viewed with considerable caution. The realization of a transceiver for such services as GSM involves many considerations that are not solved by a change from one integration technology to another.

It's also interesting that some of the things that are being said about the irrelevance of impedance-matching in modern implementations of radios seem to overlook the fundamental importance of utilizing as much of the received signal power as possible; "front-end" design is as often as much a challenge in thermodynamics as anything else. The need for filter matching is also not likely to go away just because a CMOS happens to present an essentially open-circuit (small capacitance) to the source, though it is worth remembering that many extant filters (both purely electrical and electromechanical) were originally developed with vacuum tubes in mind.

Nevertheless, the development exercises now being pursued in the arena of "RF CMOS" hold much promise, in particular, in connection with mixer design, traditionally the bailiwick of bipolar technologies (in the form of the so-called "Gilbert mixer", which has an interesting history of its own, dating to the mid-sixties) and the power-hungry and lossy diode-ring mixers. Anyone who has ever attempted to design a high-intercept (say, +30 dBm) low-noise-figure (say, 9 dB DSB) mixer in a bipolar technology knows how very difficult a challenge this is. Majority-carrier devices, used either as "linear" elements (in their saturation mode) or as switching elements (in the triode region), can provide excellent IP3, though most of the reported designs fall short of what, say, a base-station designer needs, and noise performance is not quite there yet. Similarly, while VCOs (and pre-scalers) using BJT designs are hard-pressed to achieve the ultra-low-phase noise required for many applications, CMOS is not inherently more promising, with the added concerns of a flicker (1/f) noise corner which is at a very much higher frequency than a bipolar device -- thus, more troublesome in VCOs and other low-jitter applications.

Moving away from budget-RF applications and considering other important areas of development, such as low-noise, wideband fixed- and variable-gain amplifiers, multipliers and modulators, logarithmic amplifiers, rms-dc converters and power detectors (up to 10 GHz, these days), high-precision, low-drift instrumentation amplifiers, line drivers, sensor interfaces and many more highly demanding applications for IC technology, the case for bipolar, in particular fully-complementary processes, remains very strong. As already noted several times, one of the great assets of a bipolar technology remains its high and very predictable g_m and the precision and profound utility of its "logarithmic/exponential" behavior, which pops up in all sorts of diverse and subtle ways. For example, even a humble band-gap reference leans on "translinear notions" (in the DV_BE department) and furthermore is able to reach back to the deep underlying dependence of the band-gap energy in the saturation current I_s(T) and thus in the exquisite transducer-like behavior of V_BE(T,I_C). Nothing remotely like this can be found in the CMOS transistor, whose V_GS(T,I_DS) is all but devoid of meaning.

It seems like a small thing on which to base multi-million-dollar investments.

Barrie Gilbert (IEEE Member 1962, Fellow, 1984), b. 1937, in Bournemouth, England, pursued an early interest in solid- state devices at Mullard Ltd, working on first-generation planar ICs. Emigrating to the US in 1964, he joined Tektronix, in Beaverton, OR, where he developed the first electronic knob-readout system, and other advances in instrumentation. Between 1970-1972 he was Group Leader at Plessey Research Laboratories. He later joined Analog Devices Inc. and was appointed ADI Fellow in 1979. He manages the development of high-performance analog ICs at the NW Labs in Beaverton.

For work on merged logic he received the IEEE "Outstanding Achievement Award" (1970) and the IEEE Solid-State Circuits Council "Outstanding Development Award" (1986). He was Oregon Researcher of the Year in 1990, and received the Solid-State Circuits Award (1992) for "Contributions to Nonlinear Signal Processing". He has written extensively about analog design and has five times received ISSCC Outstanding Paper Award. He has been issued over 40 patents and holds an Honorary Doctorate from Oregon State University.