As Gigabit Ethernet and OC-48/STM-16 nodes start permeating the communications industry, the bandwidth requirements on the line and across the backplane are increasing exponentially. 40-Gbit/s backplane bandwidths are commonplace today and traditional backplane bus structures are on the verge of extinction. The new buzzword is serial. The concept, while technically efficient and aesthetically elegant, is fraught with design and component selection issues of critical importance, and an example is discussed. Designers responsible for interfacing to SONET and Ethernet lines are already too aware of the stringent timing requirements associated with these standards. The cost associated with the transceivers that satisfy these requirements is a good investment, but what of the proprietary backplanes and interconnects within the system? Should they be subject to overkill too? The cost benefit tradeoff in the industry seems lopsided and we discover surprising insights when we look at the factors that influence the selection of these transceivers:

1. Timing: The ability to reliably transfer data from one point to another with minimal distortion and maximum reliability is the raison d’ýtre of transceivers. The unit time interval for each bit of data transmitted was relatively large at the 100-Mbit/s Ethernet and the 622-Mbit/s ATM over SONET nodes. At 2.5 Gbit/s the interval shrinks by about 75% which translates to an increasing dependence on the transmitter to provide low-jitter, fast-transitioning signals. These industry specifications are extremely strict for line transceivers.

This does not however impose any restrictions on proprietary links within the system. The designer should look for an effective performance vs. cost tradeoff and the emergence of silicon at 2.5 Gbit/s in CMOS promises to deliver what is necessary. CMOS in its present form may not meet the requirements for line transceivers in SONET equipment but they already have met Gigabit Ethernet specifications, which is more than good enough for proprietary links. The limited line lengths these signals have to cover (between 1 and 15 feet) are well within the capabilities of CMOS transceivers across appropriately impedance-controlled cabling/traces.

2. Signaling Levels: The transition from single ended to differential signaling has many flavors, LVDS and PECL being dominant. LVDS is limited to a maximum line speed of 622 Mbit/s by both the relevant standard and the state of technology. PECL has been dominant in telecommunications equipment and CML (current-mode logic) is rapidly penetrating this space. Signaling will trend towards lower signal swings as the buffer technology improves. The interaction of CML and PECL transceivers is possible through ac coupling.
3. Power: The 2.5-Gbit/s node has traditionally been dominated by GaAs and bipolar transceivers and the inherent power consumption associated with these processes has been a barrier to their widescale deployment. CMOS transceivers promise to break through this barrier presenting a solution to the thermal and power sourcing issues that plague present-day high-speed designs.
4. Ease of Intergration: To be perceived as a long-term player, any technology needs to continually decrease in its cost and increase in its scale of integration. The GaAs and bipolar processes make it extremely difficult to achieve a high level of integration. With the emergence of CMOS technology for 2.5-Gbit/s transceivers, both horizontal and vertical integration is now a definite possibility opening up new vistas to the designer in terms of vertical integration. Crosspoint switches with serial transceiver ports would be such a new possibility with the emergence of this technology.

Of course this process would lend itself to multiple applications besides proprietary point-to-point links. Among those planned by Texas Instruments, for example, are IEEE-1394 physical layer devices, FibreChannel physical layer devices, serial backplane transceivers, etc.

A typical example of how a backplane across multiple boards would be implemented using this technology can be illustrated as follows: Assume that the maximum bandwidth any card would need to transmit across a backplane is 2 Gbit/s. This may be implemented using traditional backplane technology (see Fig. 1.)

The above implementation, for example, would require 50 parallel lines, each with its own bus transceiver logic running at 40 Mbit/s to achieve the 2 Gbit/s rate. It would also require bus arbitration to allow a card to use the full bandwidth. This implementation is riddled with problems such as bus-loading issues, EMI considerations, interference, signal ringing and extremely high cost. The better alternative would be a serial configuration (see Fig. 2.)

In that architecture (Fig. 2, again) we can see that the multiple backplane parallel transceivers are replaced by one device. This translates to an ideal transmission environment, which is point-to-point single-loaded. The restrictions on the maximum I/O bandwidth on the backplane are not arbitration constrained. If a longer transmission distance was needed, this architecture would also offer the option to interface any number of standard fibre-optic transceivers in the market today. The cable and connector-assembly issues are simplified as well, with the number of pins being reduced drastically across the backplane. This reduction is more than a decrease in the number of signal pins because multiple ground pins would be eliminated with the removal of the common ground reference between cards.

Above all, the most significant benefit these transceivers would provide is the elimination of interchannel skew. A point-to-point implementation with clock recovery at the receiver has no skew associated with it. With serial technology being extremely scalable, a move to even higher data rates will preserve this advantage.

Future Trends In Transceiver Technology: OC-192/STM-64 nodes at 10 Gbit/s are the logical successors to 2.5-Gbit/s and indeed DWDM has already enabled the 10-Gbit/s market. This leads us into transceiver requirements of 10 Gbit/s. In CMOS these could initially take the form of multichannel synchronized 2.5-Gbit/s devices, with advances in process technology leading us to 10 Gbit/s over a single pair. Transceivers will increasingly appear with more and more of the protocol or switching layer integrated as mixed-signal design prowess increases across the industry. The power/cost vs. bandwidth bar will continually be lowered with a major step-function appearing over the next two years.

Summary: CMOS is changing the face of the industry in transceiver technology. Speed nodes traditionally dominated by GaAs and bipolar processes are being invaded by CMOS. Applications driving this market are serial backplanes and proprietary point-to-point links. CMOS offers greater integration, less power, more flexibility, smaller size and most important, a quantum cost reduction. CMOS technology will continue to enable the I/O transition in communications equipment and drive value into the market place. GaAs and bipolar processes will continue to play at extremely high-end speeds but CMOS seems set to compete effectively.

About the Author

Sameer Vuyyuru is the Worldwide Marketing Manager for Texas Instruments' Telecommunications and Networking Bus products. His duties include marketing TI's 2.5-Gbit/s CMOS technology in addition to other high speed buses. He has also worked in TI's Mobile Computing Architecture Labs as an electrical lead engineer.