LVDS is a data interface standard that is defined in the TIA/EIA-644 and the IEEE 1596.3 specifications. It is essentially a signaling method used for the high-speed transmission of binary data over copper using a lower voltage swing than other transmission standards (see Fig. 1.) This low-voltage differential scheme is what delivers higher data transmission speeds and inherently greater bandwidth at lower power consumption.

General purpose LVDS technology addresses point-to-point physical layer interfaces. These include intra-system connections via printed circuit board traces or cables. The ultimate rate and distance of LVDS data transfer is dependent on the attenuation characteristics of the media and the noise coupling to the environment.

Outside the scope of the TIA/EIA 644 standard lies multipoint LVDS which supports backplane applications such as proprietary buses and small computer system interface or SCSI. (SCSI is a high-performance peripheral interface that distributes data independently of the host computer. It’s used with devices such as hard disk drives, tape drives etc.)

An interesting application of LVDS is realized by combining serializer/deserializer PLL technology with LVDS signaling. This configuration allows current chipsets to interface backplane busses running at speeds up to 622 Mbit/s, which fall into the LVDS realm. The multiplexing of parallel TTL/CMOS data allows the data to travel over a narrow bus width between the two stations, while using fewer and more economical interconnect wires results in cost savings.

LVDS represents a significant decrease in power to comparable high—speed transmission devices such as PECL. LVDS has a center at 1.2 V and the 250 mV differential signals provide the advantage of reducing noise impact such as crosstalk and EMI when transmitting very high data rates over wire. LVDS has demonstrated low power spectral content (EMI) than competing technologies such as RS-422, PECL, and TTL. This translates to less noise on a cable in point-to-point transmission applications. In addition, LVDS supports an input voltage range of 0 V to 2.4 V, which allows for >1 V shifting of the signal center (from 1.2 V) due to ground potential differences and noise. This provides a reliable margin against ground shifting that might occur between transmitter and receiver on the serialized links.

In a bus application (see Fig. 2) TTL data and clock coming from bus transceivers, which interface the backplane bus, arrive at the parallel inputs of the serializing transmitter. The clock associated with the bus is also connected to the device. The on-chip PLL synchronizes this clock with the parallel data at the input and the data are then multiplexed into three different line drivers, which perform the TTL to LVDS conversion. The clock is also converted to LVDS and presented to a separate driver. This LVDS data and clock are presented at the deserializing receiver, which recovers the LVDS data and clock and performs a conversion back to TTL. Data are then demultiplexed into a parallel format. An on-chip PLL synchronizes the received clock with the parallel data and then all are presented to the parallel output port of the receiver.

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As with any high-speed technology, LVDS requires adherence to certain design rules. LVDS, as documented in TIA/EIA-644, can have signal transition time as short as 260 ps turning a printed circuit board trace into a transmission line in a few centimeters. Care must be taken when designing with LVDS circuits.

1. If the LVDS PCB trace is more than 2 cm in length between the transmitter output pins and the connector, the PCB must be constructed to maintain a controlled differential impedance near 100 W.
2. The physical length of each trace between the transmitter outputs and the connector should be matched to within 1 mm of one another. This usually requires mitering of the traces.
3. At any cut point in the interconnect the differential characteristic impedance should be between 90 W and 130 W.
4. Use polyethylene, polypropylene, or Teflon insulation in either round or flat cables and maintain uniform distances between the conductors in a signal pair.
5. Twisting of the signal pairs is recommended but not mandatory.
6. Termination at the far end of the interconnect from the transmitter is mandatory.
7. Use thick-film leadless (0603 or 0805) chip resistors.
8. The distance and insulation between the signal and return conductors in a pair should be uniform.
9. Any parasitic loading (capacitive) must be applied in equal amounts to each line.
10. A stub is any conductive path(s) connected to the cable conductors or PCB traces between the transmitter and receiver. A stub should be as short as possible but no longer than 2 cm to 3 cm.
11. The maximum recommended cable length for non-encoded non-return to zero (NRZ) signaling is when the 10%-to-90% rise time of the signal at the termination is 8 ns for a 65-MHz clocked system. (The maximum recommended rise time for other clock rates may be calculated from tr < 1/[2f CLK].)
12. Keep the physical length of the signal pairs in the cable and PCB traces as close to the same as possible.
13. The skew between signal pairs in good quality manufactured cables can range from 40 ps/m to 120 ps/m and should be specified by the vendor. A lower number is better.
14. It is advisable that exposed connectors have pins recessed from the shell to prevent casual contact and discharges.
15. It is also a good idea to have the ground pins longer than the signal pins in order to make the ground connection first and equalize the ground potentials before signal connections.

If the above rules are observed, LVDS technology offers the system designer a low cost, low power alternative to traditional bus transmission methods.

The LVDS chipset is ideal for applications needing high-speed data transfer, common mode noise rejection, and low power consumption. These applications are common in the telecommunications industry. The emergence of new broadband transmission equipment and next-generation cellular infrastructure base stations require that backplanes speeds increase to rates much faster than those seen in past architectures. The same concept also finds applications in Host Digital Terminals, Optical Network Units, Fiber Nodes, Broadband Switches, Tandem Switches and Digital Cross Connects.

About the Author

Sameer Vuyyuru is the Worldwide Marketing Manager for Texas Instruments' Telecommunications and Networking Bus products. His duties include marketing TI's 2.5-Gbit/s CMOS technology in addition to other high speed buses. He has also worked in TI's Mobile Computing Architecture Labs as an electrical lead engineer.