The performance of DSPs is increasing steadily as Mooreŭs Law -- the doubling of the number of transistors every 24 months -- continues to hold true for the electronics industry. As the size of transistors continues to shrink, they also become faster, and speeds that were once unimaginable are now achievable. Today, designers of DSP-based systems have thousands of MIPS at their disposal, which allows them to create revolutionary new products.

Applications beyond the traditional voice and audio band are only realizable if data can be efficiently transferred into DSP memory for algorithmic manipulation. Many of these systems require data converters to transfer data at high rates into the processor, as well as to interface the processor to the analog domain. For these applications, parallel data transfers must be employed instead of the slower serial methods.

As processors approach data transfer rates of a Msample/s, processor bottlenecks start to appear and they limit the transfer rate. By closely examining these bottlenecks, designers can make certain improvements to the data converter that allows for a more efficient use of the DSP.

The Issue: Understanding Interrupt Latency
In a typical parallel data transfer between an ADC and a DSP, the ADC is memory-mapped and can be treated as either a synchronous or asynchronous memory location that must be read. As such, the ADC will initiate the transfer by sending an interrupt to the processor. The time between the interrupt and the read-enable signal is defined as the interrupt latency which is determined by several factors within the processor.

For pipelined processors, the interrupt must work its way through the pipeline for execution. Then, the interrupt service routine (ISR) has two potential implementations. One option is to handle the interrupt in software, and the other is to directly use the direct memory access (DMA) controller. If a software interrupt service routine is implemented, multiple factors such as cycles per instruction, flow implementation and memory location will determine the latency. For instance, if the ISR is stored in external memory, the external memory interface (EMIF) pipeline must be filled before access. Also, if the EMIF is busy, the previous task must complete before the ISR can be read into the processor. If available on the processor, using the DMA controller configured directly to the interrupt is the preferred choice. Modern DMAs are flexible enough to allow configuration of one channel to directly control the ADC data transfer. But even if the DMA is used, interrupt latency is still present.

For example, the TMS320C542 DSP running at 40 MHz without DMA will have a latency of approximately 400 ns. For the TMS320C6201 DSP running at 160 MHz and implementing DMA, the latency is 56 ns. Interrupt latency is deterministic in nature and cannot be determined from a data sheet. To help alleviate this potential bottleneck, many DSP makers provide applications reports that contain actual latency numbers for each type of read that the DSP will perform. The interrupt latency still remains a significant issue even when the system designer implements an ISR. Fortunately, leading-edge manufacturers of data converters are implementing ways to reduce the latency issue.

The Solution: ADCs with FIFOs
The fortunate aspect of latency for system designers is that elegant solutions are appearing that minimize its effect and improve data transfer rates. One way to minimize the effects of processor latency involves the use of first-in/first-out (FIFO) memory in the ADC, which optimizes the amount of data transferred each time the DSP receives an interrupt.

Without FIFO memory in the ADC, the DSP is interrupted each time a word or a sample of data is ready to be transferred. The quoted latency of 400 ns in this example is eight times larger than the 50 ns time it takes the DSP to read the sample data. As a result, only 11 percent of the DSPŭs processing time is spent reading data and 89% of the time is spent setting up for the read (illustrated in Fig. 1.) By integrating a small FIFO onto the ADC, the data can be bundled together before interrupting the processor; thereby reducing interrupts by a factor of the FIFOŭs depth, or 14x in this example. In other words, having access to FIFO memory allows the interrupt latency to be distributed over the useful depth of the FIFO. The interrupt latency of 400 ns is still present, but by using a FIFO buffer in the ADC, up to 14 words of data can be transferred with only one interrupt. The DSPŭs time to read 14 samples has been reduced by a very significant 83% (see Fig. 1B.)

Fig. 1: Effective latency reduced by the FIFO in the ADC

Circular FIFO Buffer Enables Improvements
So now that we have determined that ADCs with integrated FIFOs are beneficial to data transfer rates, lets take a closer look at the most effective implementation of the FIFO.

A useful FIFO requires the ability to read and write to the FIFO at the same time. Various processors optimize with different FIFO depths, so a programmable trigger in the FIFO is needed to assure any particular ADC can be optimized for any number of DSPs. To enable continuous time systems for a range of processors, the FIFO must have three separate pointers: read, write and programmable trigger level. Implementing a circular FIFO allows the user to always have access to the most recent data, which can be beneficial in asynchronous, event-driven applications, such as anti-collision systems.

TIŭs THS1206 ADC demonstrates how a programmable trigger level might be implemented. The trigger level is defined as the number of words that are read into the FIFO before initiating an interrupt to the DSP. With a programmable trigger level, this depth can be adjusted to optimize the transfer rate depending on the performance of the DSP or the application.

In most systems, the optimum trigger level will be one-half the FIFO depth; intuitively, this makes sense since half the FIFO will be filled before the pointer reaches the trigger level. Once the pointer reaches the trigger, data in the first half of the FIFO will be read into the DSP while the new data is being stored in the second half of the FIFO. The circular nature of the FIFO allows this to continue indefinitely. The conversion values are written automatically into the FIFO, while the reading from and the writing into the FIFO is entirely controlled by the ADC and can occur asynchronously to each other.

In the THS1206 the FIFO operates with a selected storage depth of eight words (see Fig. 2.) Initially the trigger pointer looks to position eight. The read pointer looks to position one, while the write pointer begins initially to write into location one and is incremented with every conversion value. The write pointer starts at position seven. With the next increment of the write pointer, the FIFO reaches its trigger pointer, which initiates the control signal DATA_AV (data available) and interrupts the processor to indicate data is waiting to be read. The block size to be read is always equal to the setting of the trigger level. In this example, the block size is eight.

Fig. 2: Circular FIFO Buffer -- THS1206

Calculating the Maximum Transfer Rate
Three basic factors determine the maximum transfer rate from the ADC with an integrated FIFO to a DSP. An analysis of these factors will help system designers match the capabilities of the ADC, DSP and FIFO trigger level. These factors are:

1. The maximum speed or conversion rate of the AD -- for example, the THS1206 is specified for a maximum conversion rate of 6 Msample/s. This limit is usually fixed and treated as a constant, such as f(THS1206) (see Fig.3.)

2. The length of the ISR -- calculated in frequency as f(ISR) = 1 / (T_latency + T_read) where T_latency = latency of processor (described earlier), T_read =( # of FIFO words read * processor read time)

3. The frequency at which valid FIFO data is overwritten -- Calculated in frequency as f(overflow) = (FIFO Depth - FIFO Trigger) / TDread1, where TDread1 = Time between DATA_AV valid and the end of the first FIFO read.

The minimum of the above three criteria will determine the maximum data transfer rate in the system. In the example illustrated (Fig. 3, agin) a THS1206 ADC is connected to a TMS320C542 DSP. The plots are the maximum sampling rate versus the selected FIFO trigger level. The three criteria listed above are plotted on the graph:

1. f(ISR), the frequency of the ISR which increases with trigger level depth,
2. f(Overflow), the curve defining overwriting of unread data. This decreases with an increasing trigger level. (i.e. fewer words left in the FIFO will be overwritten sooner),
3. f(THS1206), the maximum sampling rate of the ADC.

In this example the maximum speed of the THS1206 can only be achieved if a trigger level of eight is chosen for a 16-word FIFO. At a trigger level below eight, the data transfer is limited by processor latency. As the trigger level is set greater than eight, overwriting of unread data starts to limit the data transfer rate. This results in a 6x improvement in data transfer rate by adding the 16-word FIFO to the ADC. As faster processors with DMA are used, it can quickly be shown that the ADC sampling rate of 6 Msample/s limits the data transfer rate.

Fig. 3: Max. Sampling Rates Vs. FIFO Trigger Level

Improved Performance Allows New Applications
The explanations and examples used in this article show that the way data converters and DSPs transfer data will have a significant effect on the overall performance of a system. System designers will find that the speed of these data transfers can be optimized when the data converters and DSPs have features and capabilities that complement each other. This requires an intimate knowledge of both DSP and data converter technology.