Video I/O interfaces on consumer equipment used to be as simple as an RCA (phono) jack for composite video (NTSC or PAL) and maybe also S-Video on the small circular Mini-DIN connector. Now PC and TV applications are converging, requiring one box (set-top box, TV set) to process signals that were originally used in different environments. Then there is digital high-definition TV (HDTV) creating the need for new video interfaces...

There are essential differences in the analog representations of graphics (PC) signals and video (TV) signals for standard-definition (SD) TV or HDTV. While digital processing is present inside the box, today's video interfaces between consumer equipment are in all but a few exceptions analog. This column highlights differences between these video/graphics formats to help the designer in choosing the right ADC for his imaging system.

An Amalgam of Formats

In a previous column (http://www.chipcenter.com/analog/c025.htm) we discussed the difference between the analog SD composite and the recently standardized component video interface (CVI) for digital TV (DTV.) Such a CVI input is found today on ‘HD-ready' displays and can accept input from a component video source, such as a DVD player or digital set-top box. Component video presents an inherently better video quality than NTSC/PAL that becomes apparent especially on large-screen displays:

• no cross-color/cross-luminance artifacts, common artifacts in composite video, resulting from the spectral interference between the luminance (gray-scale, Y) signal and the bandwidth-limited chrominance signal that is modulated on a sub-carrier in between components of the Y spectrum.
• less chrominance noise, worsened in NTSC/PAL by non-linearities in the sub-carrier modulation/demodulation of chrominance.
• no color hue shifts, due to a slight offset in subcarrier phase between the receiving NTSC decoder and the original encoder (the later developed PAL system resolves this artifact.)
• overall higher sharpness, since the bandwidth (especially of chrominance) is limited in NTSC & PAL.

While the signals on the CVI for broadcast digital TV (DTV) are similar to the VGA-type signals used in PC environments, there are also significant differences.

About Color Spaces and Blanking Levels

DTV is based on MPEG-2 compression. Since chrominance can be compressed more efficiently than luminance, the MPEG-2 compression algorithm operates in a Y (luminance), CbCr (chrominance) color space, and not a red-green-blue (RGB) space like PC graphics signals.

Fig. 1: DTV analog video line

Fig. 1 shows the analog waveform of R, G, B & Y and the waveforms of Cb & Cr. Neglecting the synchronization pulses, the signal amplitudes are constant at the video ‘blanking' level outside the active video window. Now note that this blanking level is different with respect to the active video range for RGBY channels on one hand and PbPr channels on the other (we neglect here the accents in the figure, which only indicate that all signals are gamma-corrected.) The CVI interface specifies a YCbCr color space (it is actually denoted YPbPr when the signal is in the analog domain), meaning that on two of the three channels blanking will be at ‘mid-level' (Pb,Pr) while for Y it is at ‘bottom-level'. A PC graphics interface always requires ‘bottom-level' blanking on each of its R, G & B components.

This difference has a profound impact on the circuitry around the ADC when such signals need to be digitized. Typically in video and PC graphics, signals are ac-coupled and thus require a dc-restoration or ‘clamping' circuit on the receiving end. Since the analog level during blanking is known, the clamping circuit is supposed to clamp or ‘fix' the ADC output code during blanking to a preset level. When properly designed, the clamping circuit prevents any constant or slowly varying dc shift (e.g. from 60 Hz hum) in the analog video signal from showing up in the digital domain.

Now suppose you need to design a circuit to digitize both PC graphics (RGB) and DTV component video (YPbPr). New generations of flat panel displays have additional digital processing (de-interlacing) on board to enable the display of video, next to PC graphics. This is rapidly becoming a common requirement, especially for LCD- or plasma-display (PDP) TVs.

Fig. 2 & 3 show the required behavior for the clamping circuit in each of both cases. A programmable clamp is shown: By setting the ‘clamp code', the ADC output codes during the blanking, and thereby during the active video as well, are adjusted, controlling the display's brightness. Note that the nominal levels should be different between mid-level and bottom-level clamping: ADC output code 0 (bottom-level) Vs. ADC output code 128 (mid-level.) In some applications that require a standard representation of the digitized signal, the blanking level on Y needs to correspond to ADC output code ‘16'. Programming the correct clamp code accomplishes this.

Fig. 2: Bottom-level clamping

Fig. 3: Mid-level claming (Pb, Pr)

About Synchronization and Sampling Clocks

Fig. 1 also shows a ‘tri-level' synchronization inserted on the video channels. The CVI interface implements sync-on-Y (SOY.) Since this sync includes both horizontal (HS) and vertical sync (VS) information, it is called ‘composite sync' (CS.) In PC graphics, sync signals are carried on dedicated HS & VS lines.

Another difference between the DTV CVI and PC graphics is the required sampling clocks that are generated from the horizontal synchronization pulses using a PLL circuit. The divider in the PLL feedback loop sets the ratio between the sampling clock frequency and the HS frequency (i.e. the total number of pixels per line.) Popular PC VESA formats all have <2 k pixels/line so an 11-bit divider is sufficient. However, HDTV requires e.g. 2200 pixels/line for the 1080I format used today by several U.S. broadcasters, and thus a 12-bit counter depth of the PLL divider.

About Digital Video Representations

In video broadcast, digitized component video in the YCbCr format is commonly represented in a ‘4:2:2 format.' This means Cb & Cr components are each sampled at half of the sampling clock compared to Y. This is possible since chrominance and luminance are separated in Y, Cb & Cr and the chrominance components can be bandwidth limited.

This is shown in Figure 4.

Fig. 4: 4:2:2 sampling format (YCbCr)

Both components are then multiplexed onto the same 8-bit bus, resulting in a 16-bit instead of a 24-bit interface. In a lot of cases the ADC sub-system interfaces to a video ASIC or DSP with only such a 16-bit interface. A converter supporting this output can then avoid an extra demultiplexer.

In PC graphics, on the other hand, no subsampling can be done since there is no chrominance/luminance separation in the RGB space, so a 24-bit interface is always required.

Available ADC solutions

Today single-chip digitizer ICs are on the market that include 3 analog-to-digital channels, where each channel consists of an 8-bit ADC, a programmable gain amplifier (PGA) for contrast control and a clamping circuit. These parts were designed for use only in PC graphics environments (i.e. for the digitization of RGB signals in mostly LCD monitors or projectors.) Therefore they only have a ‘bottom-level' clamping circuit, in some cases only an 11-bit PLL feedback divider and no support for 4:2:2.

TI is announcing this month the THS8083, the first flat panel display ADC capable of directly accepting both RGB and YPbPr analog formats via its configurable clamping circuit similar to that shown in Fig. 2 & 3. Also for DTV environments, TI's THS8083 includes a 4:2:2 output formatter and a composite sync separator. More information can be found on TI's web site at http://www.ti.com/sc/ths8083

About the author:

Bart DeCanne is a senior systems engineer in Texas Instruments Advanced Analog Products division in Dallas, TX. He is product champion for data converters targeted to imaging applications. Before joining TI in 1998, DeCanne was employed at Barco NV in Belgium where he worked on product development for professional broadcast and cable equipment. DeCanne holds a master of science degree in electrical engineering and a business administration degree, both from the University of Ghent (Belgium).

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