Abstract

The double data rate (DDR) bus-termination power requirements bring new challenges to the supply by requiring voltage tracking of a reference, requiring both sourcing and sinking current, and in maintaining high efficiency over a wide current range. This paper addresses these issues while presenting an example DDR design of 20 A of output current with voltage outputs between 0.9 and 1.25 V. Issues and their solutions are presented for the power supply operating as a traditional buck power stage in the sourcing mode, as well as operating as a synchronous boost regulator in the sinking mode. Regulation and control-loop characteristics of the examples are presented for both current sinking and sourcing modes. Transient load response is also presented showing output voltage variation as the current is transitioned from sourcing to sinking. Sufficient design detail is provided to form the basis for a successful DDR power supply.

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