Figure 1 shows a typical configuration of a power converter using two cascaded power stages. The first stage is a boost converter that will convert the AC voltage to a DC voltage with PFC. The output voltage of the boost stage might be as high as 385 V to meet the universal line requirements of 85-265 Vrms. The second power stage is a forward converter that steps down the boost voltage. One example of the benefit achieved by synchronizing the PFC controller with the step down converter’s controller is when the UCC3817 PFC controller is used in this kind of two-stage power system. When the UCC3817 is properly synchronized with the downstream converter, it can reduce the ripple current up to 40% through the boost capacitor [1]. Some of these controllers do not give you internal circuitry to synchronize the oscillator. However, most of the controllers do give you access to the oscillator ramp, which can be synchronized with external circuitry.

Figure 1, Two-Stage AC to DC Power Converter

Internal Oscillator of a PFC or PWM Control Integrated Circuit

Properly synchronizing the PFC controller's oscillator requires a basic understanding of the internal circuitry that creates the oscillator's saw tooth waveform. Generally, PWM and PFC controllers generate the oscillator’s waveform through a current source to charge an external timing capacitor (i.e. CT) and a hysteretic comparator that controls the charging and discharging of the timing capacitor. This internal comparator monitors the ramp voltage that can be used to synchronize the oscillator. Please refer to Figure 2 for a functional schematic of the PFC controller’s internal oscillator.

Figure 2, Functional PWM Internal Oscillator Schematic

Synchronization Circuit

Synchronization of the PFC controller's oscillator with the downstream converter's oscillator in a two-stage power system can be accomplished with three external components. These components consist of two diodes and one capacitor. Please refer to Figure 3 for a schematic of the synchronization circuitry. Note that the downstream converter must use traditional trailing edge PWM to ensure proper synchronization. A description of trailing edge PWM can be found in the UCC3817 data sheet [1].

Figure 3, Synchronization Circuit

Theory of Operation

The gate drive of the downstream converter provides the clock signal to synchronize the PFC's oscillator. Electrical components C1, Ct and diode D2 form a voltage divider that adds a synchronization pulse to the oscillator ramp when the gate drive of the downstream converter transitions from low to high. The added voltage pulse will trip the internal comparator, signaling the oscillator's circuitry to discharge CT. When the gate drive transitions from high to low, it will discharge C1 through the gate drive and diode D1, resetting the circuit. Diode D2 blocks the discharge current of C1 to ensure a clean oscillator saw tooth waveform during circuit reset. To get a better understanding of how this synchronization circuit works, please refer to the gate drive and oscillator waveforms in Figure 4 and the synchronization circuitry of Figure 3. At time T0 the gate drive transitions from low to high, causing a voltage pulse to be added to the oscillator's ramp through the voltage divider created by C1, CT and D2. At time T1 the internal peak comparator is tripped, discharging CT The timing capacitor will continue to discharge until the oscillator’s valley is reached at time T2 where the oscillator's comparator turns off, allowing the timing capacitor to begin charging for the next ramp cycle. The synchronization circuit is reset at time T3 where C1 is discharged through the gate drive and diode D1.

Figure 4, Synchronization Timing Diagram
(click on image for larger view)

Design Example

In this design example a UCC3817 Power Factor Controller was designed to be synchronized from the gate drive of a UCC3802 controller. These devices could be used for a two-stage power system similar to the one represented in Figure 1. For proper synchronization it is important to select the UCC3817 timing components to set up the oscillator to run at frequency that is 20-30% less than the UCC3802's oscillator. For this design example the timing components for Rt and CT were selected for the oscillator of the UCC3802 to be operating at 100 kHz. In this example the UCC3817 components were selected for an oscillator frequency of 80 kHz. The UCC3817 data sheet lists the following equation to select the timing components for the controller's oscillator [1]. First an 820 pf capacitor was selected for CT, which would require a resistor of roughly 11k Ohms for Rt.

After Vpulse has been calculated and the diodes needed for synchronization have been selected, the following equation can be used to estimate the required capacitance needed for C1. The diodes selected for this circuit were Fairchild 1N914 and were selected for their low diode capacitance of 4 pF. VD2 is the forward voltage drop of the diodes selected. The 1N914 has a forward voltage drop of roughly 0.7V. It is also important to know what the maximum gate drive voltage is to properly set the voltage divider. The maximum gate drive voltage is represented by (VVcc3802-Vsat). VVcc3802 is the variable for the UCC3802 supply voltage, which was set to 10 V for this design. Vsat is the saturation voltage of the UCC3802 gate drive, which the data sheet states is roughly 0.4 volts maximum at 20 mA of load current [2]. The minimum capacitance required for C1 was roughly 220 pf.

The waveform in Figure 5 shows the oscillator saw tooth waveform of the UCC3817 with a Rt of 11 kohms and a CT of 820 pf without synchronization. The oscillator was designed for a frequency of 80 kHz +/- 15%. From the waveform it can be seen that the oscillator was operating at frequency of roughly 70 kHz, which was within the design goal.

Figure 5, UCC3817’s Oscillator Before Synchronization

Figure 6 shows the gate drive and oscillator waveforms of the UCC3802 and the oscillator waveform of the UCC3817 when properly synchronized with the circuit presented in Figure 1. Channel 1 is the gate drive waveform and Channel 2 is the oscillator waveform from the UCC3802 and Channel 3 is the oscillator waveform the UCC3817. From the waveforms it can be observed that the UCC3817's oscillator is synchronized to the UCC3802's oscillator at a frequency of roughly 100 kHz.

Figure 6, UCC3802 and UCC3817 Synchronization Waveforms

To gain the benefits of reduced ripple current in the boost capacitor of an off line two-stage power system required synchronization of the second stage’s PWM controller to the UCC3817 PFC controller. This design example showed how easily a PFC controller could be synchronized with the downstream converter’s PWM gate drive. The synchronization was accomplished with three additional components and a basic understanding of the internal circuitry of a PWM controller that generates the oscillator-timing waveform.

Acknowledgments

The author would like to thank John Bottrill for his contributions to this work.

References

[1] UCC3817 BiCmos Power Factor Correction, Texas Instruments Product Data Sheet, Rev. February 2000
[2] UCC3802 Low-Power BiCmos Current-Mode PWM, Texas Instruments Product Data Sheet, Rev 03/99

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