Turning it on (the switching device, of course)

The first major decision is what control method will be employed, or what determines when the switch is turned on and off? Despite the fact that voltage mode control seems to be making a comeback lately, traditional peak current mode control, continuous conduction mode (CCM), is used for this design. Peak current mode control responds immediately to line voltage changes and provides inherent over current protection for the switching device. This type of control requires two control loops. The inner loop contains a small current-sense resistor that senses the primary inductor current ramp. This resistor transforms this inductor current waveform into a voltage signal that is fed into the primary side controller, a.k.a. the pulse width modulator (PWM). This inner loop determines the converter's response to input voltage variations. The outer control loop compares a portion of the output voltage to a reference voltage at the input of a secondary-side error amplifier in a device such as a TL431. The output of the error amplifier drives the LED of an optocoupler, which drives the transistor portion of the optocoupler. As the output voltage increases above the desired level, the optocoupler is driven on harder, sending the signal to the PWM to back off. This outer loop determines the response to load changes. On a practical note, when operating the converter at very light loads, the contribution of the current signal is so small, the converter is essentially operating as a voltage mode converter. Using the UCC3809 PWM as the controller, the outputs of the two loops are summed together and compared to a 1V threshold. When the combined signals cross this threshold voltage, the primary switch is turned off until the beginning of the next switching cycle.

Taking a peak at the current

The maximum duty cycle, DMAX, which is equal to the ratio of the maximum on time of the switch to the switching period, t_0N(max)/T, will determine the turns ratio, N = NP/NS, of the transformer due to the dc transfer function:

In the above equation, the output voltage (V_o), the forward drop across the diode (V_D), and the minimum input voltage (V_IN(min)) are all known. The voltage drop across the switch's drain to source resistance, V_RDS(on), is equal to the R_DS(on) of the switch multiplied by the primary side switch current. For now, this voltage can be estimated to be 1V. The maximum duty cycle is user-defined, for this example the maximum duty cycle is chosen to be 50%. Working through the calculation, estimating approximately 0.5V for the forward drop across the Schottky diode, N is determined to be 5. Using continuous conduction mode (CCM) as opposed to discontinuous conduction mode (DCM) reduces the peak primary current, I_PEAK, experienced by the switching device, transformer windings, and output rectifier. This current can be calculated with the following equation:

Setting the acceptable ripple current, ΔI, at one-half the peak primary current, I_PEAK/2, equation (2) can be rearranged into:

Once the peak primary current is known, the RMS current calculations for a ramp-on-a-step current waveform follow:

Equation (4) can be simplified by replacing ΔI with the already defined I_PEAK/2:

Right about now, it's a good idea to go back and get a realistic value for the voltage drop across the FET, considering the average value of the current through the R_DS(on) during each switching cycle is equal to 3/4 of I_PEAK.

A rough guide to the building blocks

Transformers: More than meets the I's!

The ripple current, ΔI, is the ramp portion of the ramp-on-a-step current waveform. Given the ripple current as one half of the peak primary current, the primary inductance, L_P in Henries, can be determined using equation (5):

The ferrite core should have high saturation, low residual flux density, and low losses. The core material is dependent upon the switching frequency and the minimum core size is limited by the saturation flux density, B_max = B_sat. Hysteresis loss is minimized in this design by restricting the flux density swing to 800 Gauss. A rough idea of the core size required is given by equation (6).

where AP is the core area product in cm⁴, k is the winding factor which is equal to 0.2 for a continuous mode flyback, and B_sat can be assumed to be equal to B_max, in Teslas (T), Aw is the winding area and Ae is the effective core area, both in cm², of the selected core.

Now that you have a particular core in mind, it needs to be wound. Winding a core is an art in itself; winding resistance, eddy current losses, inter-winding capacitance, coupling, leakage inductance, skin effects, and isolation requirements all come into play. For more information, refer to the Texas Instruments Power Management web page and click on Training in the Support box. Under Seminar Materials there is a valuable reference called the MAGNETICS DESIGN SECTION written by Lloyd Dixon^[2]. Determining the minimum number of primary turns, N_P, and secondary turns, N_S, is a good place to start.

Selecting a core material with high permeability, µ, is not crucial because the energy stored in the flyback transformer is actually stored in the air gap, where the relative permeability, µ_r, is equal to 1. Gapping the core also reduces the residual flux density. The size of the air gap, in centimeters, is calculated by applying the following equation:

The permeability of free space, µo, is equal to 4π10^-7H/m. This gap is evenly distributed between the center post and two outer legs of the EFD30 core. The core is wound with magnet wire: two strands of 21AWG in parallel for the primary turns, the first layer wound closest to the core, the second layer over the four parallel strands of 18AWG magnet wire used for the secondary windings. This sandwich approach maximizes coupling and decreases eddy current losses and leakage inductances, but care must be taken not to substantially increase interwinding capacitance.

FETs don't fail me now

Even the best transformers will have some amount of leakage inductance. What this means to the MOSFET switch, or Metal Oxide Semiconductor Field Effect Transistor (known to its friends as "the FET"), is there will be a voltage spike induced at the point of turn off. This spike could be as large as one third of the input voltage. This is in addition to the maximum input voltage and the reflected secondary voltage already across the drain and source of the device. It is best to keep this in mind when shopping around for a FET with an acceptable voltage rating. Besides the drain-to-source voltage, consideration must also be given to the average current required to charge the gate capacitance of the FET. This current can be calculated by consulting the datasheet's Total Gate Charge, Q_G, vs. Gate-to-Source Voltage (at a particular drain-to-source voltage) graph. Multiplying this gate charge, in Coulombs, by the switching frequency results in the current in question. Knowing this current is very handy when selecting a bypass capacitor for the PWM controller, since this design uses the controller's output to directly drive the gate of the FET. The bypass capacitor, CBYPASS, needs to be sized so that the input voltage to the controller doesn't dip below the undervoltage lockout threshold while supplying both the controller's operating current, IVDD, and the charge to the gate. ΔV equal to (VDD - V_UVLO), the bypass capacitance is determined:

But wait, there's more. Just because the selected switch meets the drain-to-source voltage, and the primary RMS current doesn't exceed the rated maximum continuous drain current, and the PWM actually puts out enough current to charge the gate, doesn't mean the FET won't burst into flames, spreading death and destruction all over your circuit board. The losses in the FET will determine whether the converter will operate efficiently or just be a contributor to global warming. The on-resistance of the FET will have a significant impact on the conduction losses of the device. The conduction losses are equal to the square of the RMS current multiplied by the R_DS(on) at a particular operating temperature. Switching losses result from the drain current and drain-to-source voltage overlapping for a brief period of time during both turn on and turn off. During turn-on, this is due to the drain-to-source voltage not falling from its V-DS level until after the "Miller" capacitor begins to charge, which overlaps with a drain current that may be as high as one-half I_PEAK. This charging time, t_ch(on), is a function of the gate resistor, R_G, the gate-to-drain "Miller" charge, Q_gd, the bias voltage of the PWM, VDD, and the gate-to-source threshold voltage, V_GS(th), as shown:

During turn-off, the whole process happens in reverse, but the discharge time, t_ch(off), is a function of the gate-to-source voltage, approximately VDD, and this process occurs when the drain current is at I_PEAK.

The output capacitance of the FET will also contribute to the switching losses in the form of 1/2C_OSSV_DS²f_sw. The switching losses are estimated to be:

The total FET losses are the sum of the conduction losses, equal to I_RMS²R_DS(on), and the switching losses determined from equation (13).

Rectifying the situation

Because a Schottky diode's forward drop is lower than typical PN devices, it is the rectifier of choice when considering overall efficiency. Although most people think that Schottky diodes have the added feature of no reverse recovery time, the devices do make up for this with their substantial capacitance from anode to cathode. This capacitance needs to be charged and discharged every cycle and the current flowing into the device looks an awful lot like reverse recovery current. This high capacitance also has the potential to resonate with stray inductances. Basically, some circumstances may benefit more from an ultra-fast rectifier as opposed to a Schottky.

If the selected device has a maximum rated reverse voltage which is less than the reflected primary side voltage (V_IN(max) - V_RDS(on)) plus the output voltage, then the reverse leakage current will be out of spec because Schottky diodes are very leaky at high temperatures. The junction temperature (T_j) will go above and beyond its safe operating range if the load current exceeds the maximum average forward current rating. The reflected peak primary current should never exceed the peak repetitive forward current limit of the device.

Power loss in the Schottky diode consists of the summation of conduction losses and reverse leakage losses. Conduction losses are straightforward: multiply the forward voltage drop of the rectifier by the average forward current. Reverse leakage losses are calculated by multiplying the reverse leakage current by the maximum duty cycle and the blocking voltage. The blocking voltage equates to the reflected primary voltage summed with the output voltage.

Capping it all off

Flybacks are notorious for their high output ripple. The dc component of the inductor current flows entirely through the load and the ac-switching ripple divides between the load and the output capacitor. The capacitor must be chosen so that it diverts most of this ripple away from the load. To accomplish this, it's impedance at the switching frequency must be much less than the load impedance to ensure that nearly all the inductor ripple current will flow through the capacitor and not the load. The output capacitor becomes charged by the ramp-on-a-step secondary side inductor current during the primary switch off-time and has the sole responsibility of supplying the load current during the on-time of the switch. Unfortunately, these capacitors have parasitic resistance, a.k.a. ESR, which, coincidentally, is out of phase with it's own capacitance and, as a result, adds to the output voltage ripple. The output capacitor ripple current can be estimated by taking the RMS value of the combined segments of the switching cycle:

In equation (14), I_PEAKsec and ΔIsec are equal to the secondary side peak current and the secondary side inductor ripple current, respectively.

The charge, Q, on the output capacitor is equal to the positive area under the current waveform, as shown in (15):

This charge, when divided by the capacitance, C_OUT, will result in a ripple voltage. The ESR, when multiplied by the peak secondary current, I_PEAKsec, will also result in a ripple voltage. The total output ripple voltage is determined by:

Because these parameters vary widely over typical ranges of interest, always be sure to select capacitors based upon their ripple current rating and ESR at the actual temperature and frequency of the application.

Control yourself, please

Somewhere, someone probably told you to never design a flyback in the continuous conduction mode. They probably cited something about a horrible, right-half-plane (RHP) zero that should be avoided at all costs. Admittedly, there is a RHP zero in the transfer function of a CCM flyback. As an added feature, a RHP zero contributes a phase lag, as opposed to a phase lead. This means that in a flyback converter, the inductor current flows through the output only when the FET is off and the diode is conducting. Any increase in load current will require the primary peak inductor current to increase, which means the duty cycle of the FET must increase. But this results in the diode conduction time to actually decrease, which, in turn, results in a decrease in average load current, exactly the opposite of what was desired in the first place. This is only a temporary condition, for as the inductor current rises, the diode current eventually reaches the desired value. By far, the easiest approach to stabilize this situation is to close the loop at a low frequency using dominant pole compensation. Although quick and easy, this method will give you poor dynamic response.

Ultimately, the feedback loop must give you a good line and load regulation as well as good dynamic response. To do this, the transfer function must have high gain at low frequencies and high bandwidth for good transient response. The best way to approach loop stabilization is to actually measure the open loop response of the converter. The simplest way to do this is to configure the error amplifier for unity gain and add together an adjustable dc voltage and a swept sine wave from a network analyzer to the non-inverting input of the error amplifier. Then, increase the adjustable dc voltage until the output of the converter is within specification, and measure the open loop response. Make sure all of this is done at maximum load or bad things may happen to your output capacitors. You should see a RHP zero, a pole courtesy of the output capacitor and load, and a zero as a result of the capacitor ESR, and possibly a pole from the optocouple, as well as gain resulting from the power stage, current loop, and optocoupler. The objective is to have approximately 45 degrees of phase margin and at least 12dB of gain margin under nominal operating conditions. A realistic bandwidth to shoot for is one-tenth the switching frequency, but may be further limited by that RHP zero. To accomplish these goals, a type II amplifier was used, adding a pole, a zero, and gain as needed.

If the error amplifier can't be configured for unity gain, another method, outlined in Practical Design of Power Supplies ^[3], would be to close the loop using a Type I amplifier with a large capacitor for compensation in a closed loop configuration, measure the loop, then subtract out the effect of the capacitor. This approach works because the power stage has a fixed gain at low frequencies and can always be stabilized with a low enough bandwidth.

Wrapping it up

The following schematic implements all the building blocks for designing the power stage of a flyback power supply as outlined in this paper. The controller used is a UCC3809 Economy Primary Side Controller that has added features such as soft start/shutdown, undervoltage lockout, programmable maximum duty cycle, accessible 5V reference, and low startup current. The primary side includes slope compensation and leading edge blanking for the current sense signal. Despite all these features, this controller is still very small and cost effective.

click for larger image

Figure 2. Isolated 50W Flyback Converter utilizing the UCC3809. The switching frequency is 70kHz,VIN = 32V to 72V, VOUT = +5v, IOUT = 0A to 10A

References

[1] Lisa Dinwoodie, Design Review: Isolated 50 Watt Flyback Converter Using the UCC3809 Primary Side Controller and theUC3965 Precision Reference and Error Amplifier, Texas Instruments Application Note U-165, 1999.

[2] Lloyd Dixen, Magnetics Design for Switching Power Supplies, http://www.ti.com/, Analog and Mixed Signal > Power Management > Training > Seminar Materials, 2001

[3] Ron Lenk, Practical Design of Power Supplies, IEEE Press, McGraw Hill, 1998.

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