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The Design of 100Mbps to 660Mbps BUS LVDS Serializer/Deserializer for 3G Base Stations
by Lin Wu, Fiber Optics Business Unit, Texas Instruments, Inc.

This article presents the implementation of BUS LVDS SERDES for 3G base stations. This Serializer/Deserializer SERDES incorporates a fully integrated PLL with wide operation range and a digital DLL based Clock and Data Recovery (CDR). The chip set application is first introduced followed by the design details of each major block for this SERDES. This article is intended to provide some insights into implementing such LVDS SERDES to enable more robust data transmission in 3G base stations.

Introduction
3G mobile communications, such as W-CDMA, EDGE, and CDMA2000, promise media-rich, high-speed Internet access using cell phones. Cellular base stations will need to process and distribute exponentially greater amounts of digital data. Inside the base station, data moves at high speeds across backplanes, through cables, and within circuit boards. Low voltage differential signaling (LVDS) will be the signaling standard of choice for delivering this data since it can greatly minimize space, noise, and power and therefore reduce the cost [1] [2].

While LVDS is designed for point-to-point communications typically over balanced, controlled-impedance media of 100 ohms, Bus LVDS (BLVDS) technology is optimized for multi-point cable and backplane applications. It differs from standard LVDS in providing increased drive current to handle double terminations that are required in the multi-point application. In this article, the design of such BLVDS SERDES for 3G base stations will be discussed. These two BLVDS SERDES chipsets SN65LV1021/1212 (100Mbps ~ 400Mbps) and SN65LV1023/1224 (300Mbps ~ 660Mbps) can both be used in the bus configurations shown in Figure 1.

Figure 1. Bus Configurations: Point-to-Point, Multi-Drop, and Multi-Point

BUS LVDS SERDES ARCHITECTURE
The BLVDS SERDES architecture is shown below in Figure 2 [3][4]. It is a 10:1 SERDES TX/RX. The serializer functions by utilizing an integrated PLL to serialize a 10-bit wide CMOS/TTL data stream into a single bit high-speed LVDS data stream over backplane or cable while embedding two clock bits for framing (start bit "1" and stop bit "0"). The deserializer performs the inverse function by using the recovered clock to deserialize the incoming data and detect the framing information. In both serializer and deserialzer, a fully integrated PLL is used. On the serializer side, PLL is used as the transmit clock generator while on the deserializer side, PLL is part of the Clock and Data Recovery (CDR) circuitry to extract the embedded clock information in the incoming data stream.

Figure 2. Serializer (TX) / Deserializer (RX) System Block Diagram

The following sections first discuss PLL, as it is the most critical block in any SERDES. Then the design of BLVDS driver on the TX side will be introduced. On the RX side, the implementation of CDR circuitry is the major design challenge and therefore will be presented.

PLL DESIGN
PLL used in this SERDES has a relatively wide operation range. If the parallel word rate is from 10MHz to 66MHz, the data line rate will be from 100Mbps to 660Mbps.Considering the start bit and stop bit, equivalently the line rate should be from 120Mbps to 792Mbps. In order to reduce power consumption as well as jitter generation, a double sampling technique is used to lower the on-chip high-speed bit clock in both TX and RX. If the byte clock coming from the ASIC is TCLK, the bit clock frequency is at 6ýTCLK. Operating at half rate, the oscillator needs to work from 60MHz to 396MHz.

Six-stage ring oscillator based on the symmetric load delay cell proposed in [5] is used to cover the speed range under different process corners. This symmetric load delay cell is claimed to have very wide delay range. Figure 3 shows this ring oscillator as well as the delay cell.

Figure 3. PLL Ring Oscillator both in TX and RX

The whole PLL is an adaptive bandwidth, self-biased PLL that has fixed operation speed over the loop bandwidth ratio and a fixed damping factor that ensures fast tracking and better oscillator jitter rejection.

SERIALIZER DESIGN: Bus-LVDS Driver
Compared with other differential signaling, the reduced voltage swing in LVDS signaling (only ý350mV versus ý800mV for PECL and ý2V for RS422) allows LVDS to achieve data rates comparable to PECL (>800Mbps) while dissipating only one-tenth the power. This combination of high speed, low power, and low noise makes LVDS the ideal signaling standard for distribution in 3G base stations. BLVDS driver features a low voltage differential signal of ~250 mV and fast transition times. This allows the drivers to support applications ranging from low speeds at a few MHz (or even DC) to high speeds in the 500 MHz range and even beyond.

In order to achieve a reduced voltage swing, the BLVDS driver in this design uses two continuously operating feedback loops to set the voltage HI level as well as voltage LO level [6]. Reference HI and LO levels are generated from a separate band-gap reference. Figure 4 shows the topology.

Figure 4. BLVDS Driver

DESERIALIZER DESIGN: PLL-DLL Based Clock-Data Recovery (CDR)
The deserializer consists of four key components: a front-end differential sense amplifier to sample the incoming data stream and convert the signal from LVDS to CMOS level, CDR circuitry to extract the sampling clock for sense amplifier, a serial to parallel converter, and framing detection logic for byte alignment. In addition, logic is provided to support test modes.

As in any SERDES design, the implementation of CDR circuitry is the core of the whole deserializer. Instead of using a pure PLL CDR technique, the SERDES uses a PLL plus digital DLL based CDR to further reduce the power consumption. The PLL generates a high-speed bit clock at the correct frequency. A digital DLL further adjusts the phase of this high-speed bit clock with respect to incoming data according to the phase information detection.

The PLL generates four internal bit clocks equally spaced 90 degrees apart. These clocks are used directly to mark four sample points of the incoming receive stream. Two are considered to be data samples and two are phase samples.

Figure 5 shows the relative position of the four samples when the data eye is perfectly centered. The two phase samples illustrated are required to determine whether the sample point is leading or lagging the data eye. When the sampled data changes, the phase sample will equal either the previous or current data value depending on whether the internally derived clocks are lagging or leading the data eye. The early/late detector uses this relationship to finely tune the sample point and maintain lock.

Figure 5. Receiver Data and Phase Samples

Summary
Bus LVDS products provide designers with new alternatives for solving high-speed multipoint bus interface problems. By exploiting the benefits of LVDS SERDES in backplanes, and in other areas of high-speed signal distribution, 3G base stations will deliver higher bandwidth wireless services without requiring proportionately greater cost, size, and power. The products discussed in this article offer these benefits not only in the form of the LVDS signaling standard, but also by way of the architectures and topologies that they enable. Comprehensive familiarity with LVDS technology, products, and applications are essential tools for any engineer developing next-generation cellular base stations.

References:
[1] ANSI/TIA/EIA-644-1995, Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits, Tele-communications Industry Association, Nov. 15, 1995

[2] IEEE Std 1596.3-1996, IEEE Standard for Low-Voltage Differential Signals (LVDS) for Scalable Coherent Interface (SCI), IEEE Computer Society, July 31, 1996

[3] SN65LV1021/1023 datasheet, 10MHz to 40MHz 10:1 LVDS Serializer/Deserializer, Texas Instruments Inc., April, 2002

[4] SN65LV1212/1224 datasheet, 30MHz to 66MHz 10:1 LVDS Serializer/Deserializer, Texas Instruments Inc., April, 2002

[5] John G. Maneatis, " Low Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques ", IEEE Journal of Solid State Circuits, vol. 31, no. 11, pp. 1723~1732, Nov. 1996.

[6] Brian Young, " An SOI CMOS LVDS Driver and Receiver Pair", 2001 Symposium on VLSI Circuits Digest of Technical Papers, p. 153 ~ 154, June, 2001

Author's Information
Lin Wu is a member of technical staff of Fiber Optics Business Unit, Texas Instruments Incorporated in Dallas, TX. She received her B.S and M.S. degrees both in electrical engineering from Tsinghua University in China in 1994 and 1996, respectively. She received her Ph.D. in electrical engineering from Iowa State University in 2000. She joined TI in 1998, working on analog IC design for broadband communications and now works on high-speed serial links for fiber optic applications. Email: linwu@ti.com

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