A simple model of junction capacitance6 is given by the formula:
, where Co is the zero-bias capacitance, Vj is the junction voltage,
is the built in potential, and MJE is the grading coefficient. The transfer function of the intermediate stage is influenced by this non-linear capacitance at Vmid.
Looking at the capacitive reactance and taking y as the independent variable, we can write:
Typical numbers for TIýs high-speed BiCom 1 process include:
, and Cc = 5 pF. Using these values and setting
= 106, the plot shown in Figure 5 is drawn. Again, power series estimates are shown that use progressively more terms of the series - linear, quadratic, and cubic.
With voltage swings of about 3 Vp-p, the linear approximation is valid. At higher voltage swings, the quadratic and cubic terms are required, resulting in 2nd and 3rd order distortion products.
The effect of VA is not frequency dependent, but the effect of Cj is. Below the dominant pole of the amplifier, VA dominates the non-linearity of the intermediate stage. Above the dominant pole, the non-linearity is a combination of the two. In either case, limiting the voltage swing at Vmid (and thus Vout) is the key to linear operation.
3.5 The Output Stage - Q8 through Q11
Q8 through Q11 form a double buffered class AB output stage. The voltage at Vmid is buffered via these transistors to produce Vout. Depending on polarity, the signal path is either through Q8 and Q10, or through Q9 and Q11. The analysis is the same in either case. Assuming the polarity is positive, Vout = Vmid + VbeQ8 - VbeQ10 =
Q10 will see variations in collector current as it delivers power to the output load. Variations in Q8ýs collector current are reduced by the beta of Q10 resulting in VbeQ10 being the dominant non-linearity in the signal path from Vmid to Vout.
Again, using a power series expansion helps to highlight the nonlinear terms responsible for distortion. Expanding the natural log function around the point x = a in a power series:
. Using typical numbers for Vbe = 0.6 V, Figure 6 shows Vbe and three estimates each using progressively more terms in the power series - linear, quadratic, and cubic.
Variations of 20% or more in collector current cause the output stage to become non-linear. Increasing the amplifierýs load impedance reduces the current variations in the output transistors and helps to reduce distortion in the output stage.
A typical scenario where the output stage is designed for a quiescent bias current of 5 mA, and can deliver up to 100 mA to the load, the output current varies by a factor of 20. Under these circumstances, distortion in the output stage will dominate the intrinsic distortion of the amplifier.
4 Power Supply Bypass Capactitors
Figure 7 illustrates power supply bypassing for a high-speed op amp. The current supplied to the op amp from the power supply must pass through the distributed impedance between the power supply and the op amp. When the amplifier outputs fast rising (or falling) waveforms, the voltage drop across this impedance can cause significant voltage drop and reduce the voltage across the op amp. The transistor operation moves toward saturation, causing significant distortion. Bypass capacitors are required for high-speed operation.
The strategy shown uses bulk capacitors, typically 6.8 ýF to 10 ýF tantalum, within an inch (or two) of the power pins, along with high frequency capacitors, 0.01 ýF to 0.1 ýF ceramic, within 0.1 inch of the power pins.
The bulk capacitors store more energy but tend to have larger parasitic inductance and equivalent series resistance. For this reason, they can only provide energy at low frequencies. Due to the relaxed requirements for placement on the board, they are typically shared between several devices.
The high frequency capacitors have lower inductance and equivalent series resistance and are capable of supplying fast transients. They are located as close as physically possible to the op amp power pins.

Figure 7
5 Using Differential Amplification to Reduce Even Order Distortion
Differential signaling has been commonly used in audio, data transmission, and telephone systems for many years because of its inherent resistance to external noise sources. Today, differential signaling is becoming popular in high-speed data acquisition, where the analog -to-digital converterýs (ADC) inputs are differential and a differential amplifier is needed to properly drive them.
Another attractive advantage to differential signaling is that it significantly reduces even order harmonics. This is easy to see by using a generic power series expansion of the output voltage.
A differential amplifier has two outputs that are ideally 180ý out of phase with one another: (Vout +) = - (Vout -). The output is the differential voltage: Vout = (Vout +) - (Vout -). Assuming the amplifier is perfectly balanced, the generic expansion of each output is:
(Vout +) = K1(Vin) + K2(Vin)2 + K3(Vin)3 + K4(Vin)4 + K5(Vin)5 . . .,
(Vout -) = K1(-Vin) + K2(-Vin)2 + K3(-Vin)3 + K4(-Vin)4 + K5(-Vin)5 . . .,
where K1 through K5 are constants that depend on the characteristics of the amplifier. The odd order terms retain their original polarity, but the even order terms are always positive. Since Vout is the difference, the even order terms cancel, but the odd order terms increase by a factor of two:
Vout = 2K1Vin + 2K3Vin3 + 2K5Vin5 . . .
Balance is very important. Any imbalance in the two amplification paths will compromise the cancellation of even order terms. Symmetrical layout and matched amplifiers are required.
There are many ways to convert single ended signals to differential signals as shown in Figure 8. Some employ the use of transformers, multiple single ended op amps, and various passive components. Integrated fully differential op amps are available that are better suited to wide-band applications and can provide a more elegant solution.

Figure8
6 Loop Gain in Feedback Reduces Distortion
Figure 9 shows a block diagram of an op amp using negative feedback. The open loop gain or forward gain of the amplifier is A1A2. The loop gain is A1A2ý. e1, e2, and e3 are generalized error sources. The following discussion analyzes the output response due to the individual error sources.
e1 is amplified by the full open loop gain of the amplifier. Setting all other sources to zero:
If there were no feedback, Vout = e1A1A2, but with feedback,
if
A1A2 >> 1. Thus, e1 will be amplified by the closed loop gain of the amplifier.
e2 is amplified only by A2. Setting all other sources to zero:
If there were no feedback, Vout = e2A2, but with feedback,
if
A2 >> 1. e2 is attenuated by A1ý.
e3 is buffered by a gain of +1 to the output. Setting all other sources to zero:
If there were no feedback, Vout = e3, but with feedback,
if
A1A2ý >> 1. e3 is attenuated by the loop gain, A1A2ý .

Figure 9
The loop gain of the op amp is effective in reducing distortion in the intermediate and output stages where the distortion is highest.
7 Design Guidelines for Low Distortion
So how does one go about designing for low distortion with high-speed op amps? The following are important design considerations:
Op amp selection:
- Look for an amplifier with low intrinsic distortion, high open-loop gain at the frequencies of operation, and high slew rate.
- For VFB op amps, gain bandwidth products (GBW) in the GHz range may be required to have enough loop gain to significantly reduce distortion in the 10 MHz to 100 MHz range.
- Current feedback (CFB) op amps have much higher slew rates than VFB op amps. If the output cannot track the input due to slew rate limitations, the effectiveness of negative feedback is null and void. For this reason, CFB op amps can provide lower distortion in high frequency applications.
- For high gain applications, use de-compensated op amps. De-compensated op amps sacrifice stability at lower gain for higher GBW, higher slew rate, and lower noise. They are easily spotted in data books and selection guides by their minimum gain requirements.
- CFB op amps allow you to optimize the loop gain based on the closed loop gain of the amplifier by selection of the feedback resistor value. At higher gains, lower feedback resistors can be used without sacrificing stability (see OPA685 data sheet).
Circuit design:
- Reduce loading on the output of the amplifier as much as possible. A common practice when driving an ADC is to make a simple RC filter by placing a small series resistor and load capacitor to ground (or differentially). At the pole frequency, the impedance of the capacitor equals the resistor and the amplifier sees a significant load. Use an active filter topology (like MFB, Sallen-Key, or simply a capacitor in parallel with the feedback resistor) to make the amplifierýs gain roll-off before the pole frequency of the output RC and avoid loading the amplifier.
- Use power supply bypass capacitors. Place bulk capacitors in the 6.8 ýF to 10 ýF range within an inch of the power pins, and high frequency capacitors in the range of 0.01 ýF to 0.1 ýF within 0.1 inch of the power pins. Bulk capacitors have typically been tantalum, but high value ceramics are now available that may be viable. High frequency bypass capacitors are normally ceramic.
- Minimize output voltage swings.
- Fully differential architectures help reduce even order distortion products and are resistant to extraneous common mode noise sources. Most high-speed ADCs now use differential inputs, and differential amplification is commonly required.
- The feedback path is critical. High-speed op amps are very susceptible to the effects of parasitic capacitance. Remove ground plane(s) from under the input pins and any traces leading to them, and use minimum value feedback resistors. The idea is to avoid creating RC phase lags that decrease the amplifierýs phase margin. The resulting peaking and group delay may cause distortion of non-sinusoidal signals.
- Keep the layout tight. Use short straight traces for signal routing. For traces longer than an inch or two consider using microstrip or stripline layout techniques.
- Use double termination for best signal integrity.
Back to Article
8 Design Example
To illustrate the forgoing design guides, the circuit shown in Figure 10 is tested using the OPA687 configured in a gain of +20 (26dB). The OPA687 is a de-compensated VFB high-speed op amp with a minimum gain of +12 specification. Being de-compensated gives it significant advantages:
- Very high GBW - 3.8 GHz
- Very high SR (for a VFB) - 900 V/ýs
- Very low noise - 0.95 nV/

- High open loop gain - 100 dB @ f < 10 kHz
Figure 11 shows 2nd and 3rd harmonic distortion (HD2 and HD3) versus frequency. As frequency increases, the loop gain decreases, and parasitic capacitance becomes more dominant. The result is increasing distortion at higher frequency.

Figure 11
Figure 12 and Figure 13 show the effects of various loads and voltage swings on the distortion performance. Heavier loads and larger voltage swings cause more distortion.

Figure 12

Figure 13
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9 Conclusion
We have looked at each stage of a simplified high-speed op amp and quantified the main distortion mechanisms. Due to their dynamic nature, most of the distortion is produced by the intermediate stage and the output stage.
Reducing the voltage swings at the output and increasing the impedance of external loads will increase the intrinsic linearity of the amplifier. Higher loop gain increases the curative effects of negative feedback.
As frequency increases, the effects of nonlinear parasitic junction capacitance increase, and the curative effects of loop gain diminish. These combine to make distortion more problematic as frequency increases.
Choosing the right amplifier is key. High slew rate and high GBW are two important parameters.
Differential amplification reduces even order harmonics, and is important in driving high-speed ADCs.
Power supply bypass capacitors are very important at high frequency due to the distributed impedance between the power supply and the op amp.
- Distortion Analysis of Analog Integrated Circuits by Piet Wambacq and Willy Sansen, 1998
Kluwer Academic Publishers. Back to Article
- Intermodulation Distortion (IMD), by Christian Henn, Burr-Brown Application Bulletin AB-194. Back to Article
- Analysis and Design of Analog Integrated Circuits 3rd Edition by Paul R. Gray and Robert G.
Meyer, 1993 John Wiley and Sons, Inc. Back to Article
- Analog Integrated Circuits for Communications by Donald O. Pederson and Kartikeya Mayaram,
1991 Kluwer Academic Publishers. Back to Article
- Analysis and Design of Analog Integrated Circuits 3rd Edition by Paul R. Gray and Robert G.
Meyer, 1993 John Wiley and Sons, Inc. Back to Article
- Analysis and Design of Analog Integrated Circuits 3rd Edition by Paul R. Gray and Robert G.
Meyer, 1993 John Wiley and Sons, Inc. Back to Article
Authorýs Bio
Jim Karki is a member of the group technical staff of Texas Instruments currently working in high-
speed amplifier strategic marketing. He has more than 20 years experience in analog and digital
electronics, and has spent the past 5 years in amplifier applications and new product definition
with TI. He earned a BSEE from University of Washington in Seattle.
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