The advantages of SAR ADCs include small size, low power, low latency, and ease of use. The disadvantages for SAR ADCs include the need for trimming to achieve good performance and more stringent front-end filtering for anti-aliasing. A good example of a SAR ADC application is motor control, where you need fast sampling with no latency.

The other ADC architecture that is popular for these sample rates is the delta-sigma architecture. The delta-sigma architecture differs from the SAR architecture in that it relies more on digital processing techniques than on component matching and analog precision to achieve high performance. The main principle behind a delta-sigma architecture is oversampling of the analog input.

The main components of delta-sigma ADCs are the modulator and digital filter. The modulator is made up of a differentiator, integrator, and comparator that together comprise a feedback loop. The modulator runs at a rate much higher than the analog input signal bandwidth to provide for oversampling. The analog input is differentially (delta) compared against a feedback signal (error signal). The differential output from this comparison is fed into an integrator (sigma). The output of the integrator is then fed into a comparator. The output of the comparator simultaneously drives the feedback signal (error signal) to the differentiator and is fed into the digital filter. The goal of this feedback loop is to drive the feedback signal (error signal) to zero. The result is that the output from the comparator is a stream of 1s and 0s. The higher the density of 1s from this stream indicates that there is a higher analog input voltage; conversely, the higher the density of 0s from this stream indicates a lower analog input voltage. This stream of 1s and 0s is then fed into the digital filter that converts it from a high rate, low resolution bit stream to a lower rate, higher resolution digital output through oversampling and decimation.

Several key points should be noted about the delta-sigma architecture. First, because the sampling rate of the delta-sigma ADC is typically much higher than the analog signal of interest, the anti-aliasing filter roll off can be relaxed. This simplifies the analog front-end. Second, the architecture is inherently linear. Third, the sophisticated digital processing techniques and filtering used provide for a very high dynamic range. These techniques commonly include rejection of interference in the system, such as line frequency noise. Finally, because of the intrinsic filtering, there is always latency with this architecture. Although some delta-sigma ADC manufacturers claim no-latency, this is simply not possible. In these implementations, the latency is merely hidden using design tricks.

Implementations of the delta-sigma architecture range from very simple implementations to more complex highly integrated solutions. The more complex implementations allow for somewhat sophisticated programming of the digital filter to customize the performance of the ADC to the application.

Figure 2 shows a simple implementation of the delta-sigma ADC. The device is configured by simply writing to it through the serial I2C interface. The ADC result is then subsequently read through the I2C interface.

Figure 2: Block Diagram of the ADS1100 Delta-Sigma ADC

Figure 3 shows a somewhat more complex implementation. This particular ADC integrates more features, which simplifies the system design, but increases the complexity of the device. This device is configured through a serial interface; however, the interface is Serial Peripheral Interface (SPI). The configuration of the device is more complicated due to the additional features of the device and the ability to control the decimation. However, the basic operation remains the same. The device is configured by writing to the configuration registers via the SPI. When a conversion completes, the DRDY line goes low. This line can be tied to an interrupt pin to simplify transfer and processing of the data.

Figure 3: Block Diagram of the ADS1218 Delta-Sigma ADC

Figure 4 shows a state-of-the-art delta-sigma ADC. This ADC integrates not only analog functionality, but also a CPU. This greatly simplifies the system design and increases the complexity of the device. The ADC is configured and controlled directly by the CPU through internal registers. The advantage of this device includes full control over the modulator and digital filter, as well as digital processing capability.

Figure 4: Block Diagram of the MSC1210 Delta-Sigma ADC

The advantages of delta-sigma ADCs include very high resolution, very good linearity, no trimming, and relaxed anti-aliasing requirements. The disadvantages for delta-sigma ADCs include latency, larger size, and higher power consumption. Some good applications for delta-sigma ADCS include temperature measurement, where a very high degree of precision is needed, but the sampling rate is very low. Another application for delta-sigma ADCs is audio where very high dynamic range is needed.

Author's Bio
Robert Schreiber is the Product Line Manager for Microsystems Products at Texas Instruments. He has a BSEE from Oklahoma State University, an MBA from Western International University, and more than 10 years design and applications experience with analog and digital systems.

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