The HD-SDI retimer circuit performs critical repeater, port bypass circuit, and signal retiming functions in 1.5 Gbps HDTV digital switching and distribution systems
Applied Micro Circuits Corp. (AMCC), announced the industry's first High Definition Serial Digital Interface (HD-SDI) retimer circuit, the S8301, with the capacity to perform critical port bypass circuit functions as well as signal retiming and restoration for 1.5 Gbps HDTV broadcast video equipment. The S8301 is being jointly announced with the S8401 and S8501, the industry's first HD-SDI transmitter/receiver chipset to perform parallel-to-serial and serial-to-parallel conversion at speeds up to 1.5 Gbps.
A driving force behind HDTV's growing broadcast market, the HD-SDI S8301 data retimer and S8401/S8501 transmitter/receiver chipset provide low-cost, low-power high performance solutions for high speed digital transmissions in the broadcast studio environment.
With minimal power supply requirements (3.3V), and compact 32-pin TQFP packaging, the SMTPE 292M-compliant S8301 data retimer is used in HDTV digital signal switching and distribution systems to simplify design and speed time to market of broadcast video equipment including routers, distribution amplifiers and switching backplanes.
"The HD-SDI product family delivers leading edge broadcast video HDTV solutions and establishes a new price/performance equation in the broadcast industry," said Jack Basi, AMCC's director of marketing for datacom and computer products. "We designed the S8301, together with the S8401 and S8501 to offer a complete HD-SDI physical layer solution for the emerging HDTV studio broadcast equipment industry."
The data retimer contains a monolithic Clock Recovery Unit (CRU) which may be used alone or to implement a general purpose repeater for applications requiring a re-timed and buffered signal. As a port bypass circuit, the S8301 maintains low intrinsic jitter in the port bypass path, which is essential when used for multiple nodes in a video switch or router environment. In addition to retiming and restoring signal quality after transmission and equalization, the S8301's clock and data recovery PLL meets high jitter tolerance specifications with low jitter transfer peaking. To determine the presence of channel, the data retimer's lock detect circuit monitors run length, transition density and frequency of the selected input channel. The frequency monitor circuit checks the difference between the divided down recovered clock and the externally supplied reference clock to ensure signal integrity. If the frequency differs by more than (+ or -) 240 ppm the part will be declared out of lock; at which time the PLL will lock to the local reference clock, and poll the serial data inputs looking for data with valid frequency content.