Click here for Circuit Diagram (Fig.3.)

To see how the circuit works, assume the same + and - 25 V inputs as previously used. Again, these represent fault conditions so the new circuit should both prevent those faults from being coupled through the switch, and prevent the faults from damaging the chip. Taking the -25 V case first, N1 would see -25 V at its source and one input of the N3 sense switch would see the same. This sense circuit compares the (-25 V) input to the reference of -15 V. When the input exceeds -15 V N3 shorts it to the gate of N1, creating a Vgs = 0 V for N1, and with no enhancement it turns itself off. Concurrently, the comparator circuit with its reference of -15 V will cause the n-channel driver to go to a floating state and this cross-couples to the p-channel driver causing P1 gate to go to +15 V (off condition.) With both N1 and P1 turned off the -25 V fault condition cannot be coupled through the switch, and as there are no circuit possibilities for forward-biased diode current from the input terminal only minimal leakage currents flow.

The N2 clamp circuit will be turned on by the comparator output having sensed a fault. This will short the output terminal to -15 V through a 1 kW resistor (value actually varies with part number), a great convenience for ADC applications.

For the opposite polarity fault of +25 V at the input, the P1, P3 and P2 stages work in a similar way, turning off both P1 and N1 and preventing other than leakage currents from flowing. For this overvoltage case P2 will clamp the output to +15 V through, again, approximately 1 kW .

This scheme meets both of our criteria: No coupling of the fault through the switch, and no power-related damage occurring. The design combines the advantages of parallel (low on-resistance and rail-to-rail signal handling) and series (part self-protection and no coupling of the faults through the switch.)

When the power supplies are off, with input voltages still present, the architecture provides the same protection. When the supplies are off (Fig. 3, again) + and -15 V levels will go to 0V. Looking at the -25 V input case again, N3 sense switch will compare the -25V input to its now 0 V reference. This will cause the N3 sense switch to short the input to the gate of N1, thus still creating a Vgs = 0V for N1, and the MOSFET is still off. Neither the comparator circuit nor the clamp has power and the output will go to 0 V through its load. P1 gate will go to 0 V, and again there are no power supplies to operate the P3 sense switch, the comparator and the p-channel driver. With a -25 V input and 0 V at its gate P1 is not enhanced either. So, both N1 and P1 are off for the -25 V input and only leakage currents will be flowing.

For the +25 V fault condition, the P3 sense switch will short the input to P1 gate, again creating a Vgs = 0 V for P1. Neither P1 nor N1 are enhanced in this case, so the architecture prevents the signal from being coupled through, also allowing only leakage currents to flow. As in the -25 V case the output will go to 0 V through its load.

The design works equally well with a single supply or dual supplies, which can be asymmetrical with virtually no difference in fault protection, and no sequencing order is required.

Using the parts properly requires little special thought with family members designed to be pin-for-pin replacements of many popular, non-fault protected, switches and MUXES. Simply drop these devices into the same existing sockets to get the fault protection. This will then protect the circuits that follow, since we have seen that the faults are not coupled through the switches. The protection afforded by this family extends beyond just switches and MUXES. Circuit protectors are also offered in singles, triples and octals. Each protector is essentially the same internal structure (Fig. 3, again) and looks like a 65 W resistor for the input signal; if a fault is sensed the protector will turn itself off, isolating the fault from the load, and again only allowing leakages to flow at the input. These can be used to protect op amps, ADCs, sample-and-holds, etc.

A typical application of the 8 channel protector (MAX4507) shows it (Fig. 4) connected in front of a non-fault protected, 1-of-8 multiplexer. (The MAX338 shown might just as easily have been a DG506, or any other non-fault protected device.) The MAX338 channel inputs (N01 through N08) must never exceed the power supply values (here ý 15 V) and the output of the multiplexer is on the common pin (a resistive load is shown.) A0, A1 and A2 are the digital inputs controlling the MUX selection. The enable pin, EN, is shown connected to +5 V but it too can be driven by logic when MUXES are paralleled.

Click here for full diagram (Fig. 4.)

With the channel inputs of the MAX338 connected to the output pins of the MAX4507 they will never see more than + and -15 V, even if IN1 through IN8 see up to + and -40 V. This sub-system provides extremely good fault protection, and at the same time can switch signals up to the power supplies - in this case ý 15 V. Also, if the power supplies were to be interrupted, or shut down permanently, with input signals present, the sub-system will protect itself indefinitely.

That combined circuit (Fig. 4, again) can be replaced by a single package device, the MAX4508, (see Fig. 5.) Here the protection circuitry is built into the chip and nomenclature is the same for both, except that here the inputs are now N01 through N08.

Fig.5.

But there are some subtle differences between the two arrangements. In the series circuit (Fig. 4, again) any overvoltages present at the MAX4507 inputs are shared approximately equally. In the single device circuit (Fig.5, again) the MAX4508 must absorb these overvoltages by itself, which gives rise to a lower tolerance for max. input overvoltages. To understand this, take the very unlikely example of having opposite polarity faults appear at input terminals IN1 and IN2 in the series example, and NO1 and NO2 in the single.

Assume +40 V into IN1 and -40 V into IN2, occurring at the same instant of time. If channel 1 were programmed by the logic to be "on" (IN1 shorted to common) then the MAX4507 would limit and clamp this voltage to +15 V on OUT1 terminals (the input for the MAX338.) The voltage drop across the 4507 is 40 - 15 = 25 V, and the voltage drop across the 338 is approx. 0 V since its resistance is usually small compared to the load resistance (voltage-divider effect.) The voltage on the common will then be +15 V. Now for channel 2, it has -40 V at its input and -15 V at its output (OUT2 terminal) since the 4507 will limit and clamp the input voltage. Again, 40 -15 = 25 V is dropped across this channel. The N02 channel is not programmed to be on, so N02 to common will see -15 V to +15V or 30V across the 338 channel. So, of the possible -40 V at the input to +15 V at the common (output), 55 V in total drop, the 4507 shares 25 V of this, and the 338 shares 30 V of this.

If this same situation were to happen to the MAX4506 the full 55 V would have to be absorbed by the 4508 channel. This is outside of the recommended 40 V max. across the channel. Thus the 4508 handles + and -25 V faults, with ý 15 V power supplies, while the series circuit can easily handle + and - 40 V. Both arrangements can withstand + and -40V inputs when the power supplies are turned off.

The process and architecture used in creating this new family of products has limitations. The parts will not protect against 110 V ac or lightning damage. They are, however, effective at protecting against the normally expected fault condition cases, such as power supply sequencing problems and the usual mating up of independent power supply combinations. For these cases the family will sense the presence of a fault, shut down the switch, and prevent the fault from damaging the switch. All the family members will automatically reset themselves to normal operation as soon as the fault condition goes away.