Tri-level sync signals were added to the original analog 1125-line HDTV standard promulgated by NHK (Japan) and subsequently adopted as a SMPTE standard. Even though the new DTV (digital TV) standards incorporate the two "HDTV" standards of 720P and 1080I in the toolbox of allowable formats, the accepted analog signals that those digital signals will convert to still require tri-level syncs. Their invention was to give a faster edge for triggering, and an edge which was centered at a point which is voltage stable (0 V) and usually low noise.

Until now the complexity of generating and adding the syncs has been performed in either the digital or the analog domains of the set-top box or first-generation HDTV receivers. The analog form of generation is probably the more straightforward, but as many of these products have been in the hands of, and the responsibility of, the digital design engineers they have opted for digital generation and multiplexing to the data being passed to the final DACs.

The two DACs being produced by Texas Instruments are ingenious in using the fact that the three-channel DAC is an absolute requirement in any of these designs, and by building the sync re-generation into the part. The resulting savings are considerable in parts in the previous analog domain solution, or result in considerably less programming and reduced microprocessor loading in the digital domain solution.

The THS8133 is a 10-bit part, while the THS8134 is a pin-for-pin compatible 8-bit part. While the majority of professional uses will always involve the 10-bit solution, many consumer products will probably opt for the extremely small savings of the 8-bit part. They are both compliant with the EIA/CEMA "HDTV analog component video interface" (770-3) and the 10-bit part conforms to the 1080I recommendations (SMPTE 274M) and 720P (SMPTE 296M.)

Both parts can be operated up to 80 MHz -- 78 MHz being required for full-bandwidth analog DTV -- and the supply range can be from 3 to 5 V for the digital circuits, and requires a nominal 5 V for the analog circuits. An internal bandgap reference (see Fig. 1) is provided at 1.235 V. The input signals, which are selected at the output of the MPEG-2 decoder (off chip) and will be either in the format of GBR or YPbPr (Y, B-Y, R-Y), pass to the input formatter to select between the possible signal source formats of three-channel 10-bit 4:4:4, or two-channel 10-bit 4:2:2, or one-channel 10-bit 4:2:2. The signals then feed the channel registers and the current-steering DACs.

If the part is configured to take data from all three channels then all three DACs will operate at the full clock speed provided, and data will be clocked in at the rising edge of the clock signal. For 4:2:2 data (such as YPbPr) an internal multiplexer routes the signal to the appropriate channel of the DAC from either the 2- or 1-channel input. The Y DAC will be clocked at the full rate, while PbPr will be clocked at half the clock frequency.

The internal reference requires an external 0.1 m F ceramic. An additional capacitor is required on the compensation (COMP) terminal, and the internal reference may be overdriven by an externally supplied reference, if required.

The output is in the component video voltage ratio of 7:3 (video:negative-going sync) which has been common in all the component standards and in the PAL/SECAM encoded standards. The control of the sync insertion (from the SYNC/BLANK control) can apply conventional, unidirectional sync signals, or tri-level syncs on either just the Green (or Luminance) channel or on all three channels. There is no generally-accepted convention for syncs on a GBR output, but it is usual for sync to only be on luminance channel in the YPbPr format. The DACs can drive 1-V double-terminated into 75 W .

The full-scale current drive on each of the outputs is set by a resistor connected between FSADJ and ground (Fig. 1, again.) For 1-V outputs the drive current would be approximately 27 mA for channels with sync and about 19 mA for a sync-free channel, while a channel used to restore an analog encoded NTSC signal would drive about 32 mA for the 1.2-Vp-p signal. The sync and blanking required are formed by an additional current being superimposed to the channel(s) of choice. The timing allows for both vertical and horizontal sync trains and blanking to be added, all to the requisite specification or recommendation for the various standards.

The power supply ripple rejection ratio at the full-scale output of the DACs is 40 dB, up to 100 kHz, while the crosstalk between channels is also specified at 40 dB, which might have to be taken into consideration if the parts are used for non-standard, non-interchannel-related signals.

The parts exhibit acceptable output settling times of about 7 ns and the analog output delay is at a maximum of 9 ns, exceeding the digital processing delay.

The advent of the first real set-top boxes for DTV, including HDTV, has not yet really happened but will do so extremely quickly as prices reach consumer-acceptable levels and as the program transmission times are increased for material in the higher formats. These two products will be in the first consumer-acceptable boxes. In the higher grade offerings we would hope to see the 10-bit part used exclusively and it is not to be entirely unexpected that two parts will be used in a decoder to give the user a choice between GBR or YPbPr outputs.

There is also going to be a number of spin offs from DTV technology and we should expect to see general imaging requirements increasing in standard in the next few years. Any adopted imaging requirement will always need DACs at the output, and adopting an already accepted synchronization standard would make a lot of sense for those applications.

These are the first parts from Texas Instruments in this expansion of its interests in imaging applications. These two products offer the exclusive imagination of the sync regeneration and the first parts to offer an operational choice of other than just a 4:4:4 channel arrangement.

Both parts will be in full production in May 1999 in a 48-pin TQFP with the 10-bit THS8133 priced at $8.50 in 1000-piece lots, and the 8-bit THS8134 priced at $6.50 also in 1000-piece lots. An evaluation board is available at $230.