About the AD975x Family

The AD975x family is the industryıs first offering of CMOS low-power DACs (digital-to-analog converters) for high-speed broadband communications applications. The AD9751, AD9753, AD9755 TxDAC+ family of 10-, 12- and 14-bit converters are manufactured on a 0.35 micron CMOS process to reduce chip power consumption by 40 percent, effectively synthesizing input signal bandwidths up to 100 MHz and producing 300 MSPS operation with excellent in-band noise and distortion performance. These DACs boast a new benchmark noise floor of ı150 dBm/Hz while maintaining over 65 dB SFDR over broadband frequency spans.

In addition to superior dynamic (ac) performance, design benefits to the engineer include fewer design complications via the AD975xıs simplified I/O interface. Utilizing their two LVCMOS compatible data ports, the TxDAC+ family can interface to other standard CMOS compatible logic devices and reduce solution cost and complexity. The AD975x uses an on-chip 2x PLL/Clock multiplier to eliminate the need for an external clock multiplier.

Broadband Applications

The story here is the low power consumption and the extremely low noise performance of these CMOS parts. The middle and lower bits are implemented with current sources instead of R-2R ladders to give a high output impedance and a better ac performance for low-level signals and multitone combinations. The array is actually divided into 31 equal current sources which make up the five MSBs. The current sources are switched to one of either side of the differential output using a new architecture pMOS switch that is said to improve distortion numbers. The full-scale output current can be set between 2 and 20 mA using an external resistor to control the voltage to the on-board reference comparator. The reference control amplifier has a 500 kHz small signal bandwidth and can be used for small signal multiplying applications at low frequencies.

The reference input -- if it is used to override the internal reference -- could be a fixed external reference (to improve accuracy) or it might be a variable reference to adjust gain. The clock input can be single-ended or differential and an on-chip PLL doubles the frequency for the two buffered latches that form the data interface, so that the data are interleaved. The VCO can typically output frequencies from 100 to 400 MHz with a multiplier range control of x1, x2, x4 and x8 selected by a 2-bit input. The best noise performance is generally obtained with the VCO operating at the higher frequencies.

The AD9755, as the 14-bit leader of the family, dissipates a total of 216 mW typically with a 3-V rail and the part sampling at 300 Msample/s and an output of 20 mA. This reduces to 155 mW when sampling at 100 Msample/s, with 33 mA going to the analog section and 3.5 mA to the digital. The output SFDR ranges from 84 dB down to 60 dB. Typical of the lower number would be with the part operating at 300 Msample/s and an output frequency of 100 MHz to give an SFDR of 61 dB. Typical output noise with a 20 mA FS is 50 pA/rtHz.