ADI is expanding its PLL portfolio, and further solidifying its commitment to the RF/wireless market with the high-performance, low-cost ADF4001. This extremely stable clock generator PLL synthesizer is used to implement clock sources for the generation of very low-noise, low-jitter stable reference signals. The ADF4001 consists of a low-noise digital phase frequency detector (PFD). The ADF4001 also comprises a precision charge pump, a programmable reference divider and a programmable 13-bit N CMOS counter with the ability to provide down to a value of 1, which allows a wide-ranging division ratio in the PLL feedback counter.

Other notable characteristics of the ADF4001 are a 14-bit reference counter for selecting frequencies at the PFD input; a separate charge pump supply (Vp) for extended tuning in 5V systems; and a simple 3-wire serial interface for controlling all on-chip registers. Other key features are a 200-MHz bandwidth; a 2.7-V to 5.5-V single power supply; a typical operating current of 4.5mA; and hardware compatibility with ADI's existing PLL synthesizers - the ADF4110, ADF4111, ADF4112 and ADF4113. A complete PLL synthesizer can be implemented if the synthesizer is used with an external loop filter and voltage controlled oscillator (VCO) or with a voltage controlled crystal oscillator (VCXO).

Applications

ADI is leveraging its core PLL technology by targeting the ADF4001 for applications such as precision timing clock PLLs for synchronous optical networks; low-jitter clock generation; low-frequency PLLs for base stations; low-jitter clock source; clock smoothing; frequency translation; and for SONET/SDH, as well as ATM, ADM, DSLAM and SDM.

Analog Devices, Inc. 804 Woburn Street Wilmington, MA 01887. Tel: 781-937-1622; Fax: 781-937-1026

The ADF4001 frequency synthesizer really focuses on helping designers who need a very stable, low-jitter clock source at a winning price of about $2. It consists of a low-noise digital PFD (Phase Frequency Detector), a precision charge pump, a programmable reference divider, and a programmable 13-bit N counter. In addition, the 14-bit reference counter, allows selectable frequencies at the PFD input. A complete PLL can be implemented if the synthesizer is used with an external loop filter and VCO (Voltage Controlled Oscillator) or VCXO (Voltage Controlled Crystal Oscillator).

The ADF4001 is flexible and can help you generate GSM, WCDMA, and CDMA system clocks from a single 52 MHz Master Clock. In multi-band applications, you will need to get different clocks from one master clock frequency. For example, GSM uses a 13 MHz system clock, WCDMA uses 19.44 MHz, and CDMA uses 19.2 MHz.

Applications for the ADF4001 include clock generation, low frequency PLLs, low jitter clock source, clock smoothing, frequency translation, SONET, ATM, ADM, DSLAM, and SDM.

Availability and Pricing

The ADF4001 is packaged in 16-lead TSSOP and 20-lead chip scale packages. OEM pricing for 10,000-piece quantities is $1.91, and $1.98. The pricing is $2.16 and $2.54 for 5,000-, 1,000- and 100-piece quantities, respectively. Samples and production volumes are available now from stock.

For additional information and data sheets, please visit http://products.analog.com/