The M27218 transceiver offers the signal conditioning circuitry
needed to drive very long traces along the backplane. It uses Mindspeed's
third generation of signal conditioning (Amplif-Eye3), so it has all the
bells and whistles needed to drive very long traces - as long as 65 inches
of standard FR4 and two connectors. This is an impressive gain from their
first generation SERDES device that could drive 12 inches at 3.125Gb/s. The
signal conditioning also has gone from a simple one-level of pre-emphasis
to multi-level of pre-emphasis, and to multi-tasks and multi-levels of
multi-tasking. The company also added multiple levels of equalization
and finally they added their own recipe for signal conditioning to
complement their pre-emphasis and equalization.
The primary market for the M27218 is for the backplane, switches,
and routers used for enterprise storage and the carrier-class
equipment. Mindspeed developed this transceiver in response to
requests by customers whose older technology had reached its
limit. These customers were using Low Voltage Differential
Signaling (LVDS) technology, which was the best out there about
3 or 4 years ago. Now they had problems:
- They needed to cover the range from 622Mb/s up to 2.5Gb/s to
support OC-12 to OC-48.
- They needed the capability to handle very long strings of zeros or ones.
- They needed to modify or adapt the interface from LVDS to whatever
can handle 2.5Gb/s speeds because the LVDS that they were using couldn't
handle 2.5Gb/s. This means they would have to change to a technology
that runs at those speeds such as Current Mode Logic (CML) or Low Voltage
Positive Emitter Coupled Logic (LVPECL), and they incur the costs to make those
upgrades. They wanted the capability to upgrade without losing their older
technology.
The M27218 was developed to address those issues. It can adapt and sense
the interface. Additionally, it behaves like an LVDS at lower speeds and
at higher speeds it can behave like a CML. This is no trivial accomplishment
because today's SERDES technology can't accommodate parallel data across the
same data path, and it doesn't simultaneously run across a wide range of
frequencies.
To handle the long strings of zeros and ones, Mindspeed uses either AB10B or
6466 technology. It codes or scrambles the data so there are enough transitions
from 0 to 1 enabling the PLLs to detect a signal and recover the data. Today
the most stringent coding occurs with SONET streams that potentially
could have 72 consecutive zeros. When you get that many consecutive zeros the
PLL will lose its lock and won't be able to recover data.
This product is important for carriers because the biggest investment for
carriers is in port cards, even as the requirements for throughput and speed
increase. As carriers try to scale up to handle OC-12 or -48 or -192, they
also need to modify line cards to handle those speeds. Inside the line card
is an ASIC that interfaces to a backplane at 622 Mb/s, and goes to the switch
and interfaces to the port card through the 622 Mb/s LVDS line. The Mindspeed
27218 sits between the ASIC and the backplane, the switch and backplane, or
between the switch and the port card. With that position users can maintain
the same type of traffic and they don't have to overhaul the whole system,
re-architect the system, or change all their port cards to run at the higher
speeds.
The device does 4:1 or 1:4 serialization and deserialization so it can map 4
incoming LVDS (parallel) signals into one high-speed signal (serial), which
can be LVDS or CML, depending on the backplane interface. Also, it has a
pass-through mode to support the legacy, low-speed port cards that have
622Mb/s. Additionally, the device can be configured per channel. So one
channel could be running at 622Mb/s and another could be running at 2.5
Gb/s.
The M27218 has some other worthwhile features including: built-in impedance
termination resistors, diagnostic testing capabilities, loop-back capabilities
that generate patterns so it can test adjacent devices, a self-test of the
SERDES, and there's a Serial Peripheral Interface (SPI) that allows the CPU
interface to program all the features, manage all the controls, get all the
indicators from the device, and set up all configuration settings.
Compared to other competitors power consumption, this chip fares very well.
The entire octal consumes 2.5W of power compared to some quad chips that
consume 3W.
Mindspeed says that they managed to get power dissipation down to such low
levels with their unique PLL technology and because the device does a lot
of function sharing. The company uses a 0.18-micron process technology which
helps lower the power. However, they claim that the ability to share some
circuitry is the key to reducing the needed power inside the device,
especially as they get into higher levels of integration.
The M27218 Octal SkyRail SERDES transceiver will sample in July and volume
production will begin in the fourth quarter of 2002. Packaged in a
23mm-x-23mm, 324-pin HSFBGA, the M27218 OEM price is $109 in volumes of
1,000.
For more information click here:
Product Brief.