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Agilent to Present Company's Newest A/D Converter—the Fastest in the World—at ISSCC

The manufacturer says . . .

ChipCenter's Paul O'Shea says . . .

In November, 2002, Agilent unveiled a new line of Infiniium oscilloscopes, a product essential for R&D designers in communications, semiconductors, and computing. The power behind the latest version of these oscilloscopes is the fastest A/D converter circuit in the industry. That A/D converter, the key to unlocking untold time and cost savings for high-tech designers, is a creation of Agilent Laboratories, Agilent's central research facility. The work was so revolutionary that the scientists behind it were awarded the Barney Oliver prize, Agilent Labs' annual award for contributions to Agilent Technologies that demonstrate outstanding qualities of creativity, innovation, technical depth, and business value. Agilent's Brian Setterberg will be presenting a technical paper on the new A/D converter, "A 20 Gsamples/s 8-bit A/D converter with a 1 MB memory in 0.18 micron CMOS," at the ISSCC Conference. Agilent Technologies, Inc. Agilent Laboratories 3500 Deer Creek Road P.O. Box 10350 Palo Alto, CA 94304 Agilent Web

What makes this A/D converter so interesting aren't just the very impressive specs, but the story behind how it was developed for the end product that was so thoroughly reviewed by ChipCenter's Alex Mendelsohn. True, the converters were designed specifically for Agilent's newest Infiniium oscilloscopes, but the company was able to keep parts costs down, energy consumption at a minimum, and still provide the fastest sampling rate—a real eye-opener for other companies to consider. This was cooperation and ingenuity between the two highly respected groups—the Agilent Labs team and Agilent's test and measurement division—taken to a new level. The lab crew, after all, typically took on the most challenging project. They first presented their idea to enhance performance dramatically for a new high-end digital oscilloscope. The new A/D converter, which the lab crew promised would provide at least a five-fold improvement in system bandwidth and sample rate, would be the critical component in the new oscilloscope. Agilent Labs presented this contribution in a paper at the 2003 IEEE International Solid-State Circuits Conference (ISSCC). Unlike competing A/D converters using the fastest semiconductor process possible, the Agilent team used mainstream digital CMOS, which substantially reduced manufacturing costs and system power consumption. In effect, the Agilent Labs' team built the world's fastest A/D converter using relatively slow transistors, albeit in innovative ways. But to make this significant contribution, and to do so in a timely manner, the development teams would take yet another risk. Instead of Agilent Labs taking its traditional role of developing key technologies in advance of product design work, it did something it rarely does: put itself in the critical design path for the overall project. That meant the division's product schedule would be tied directly to development work coming out of Agilent Labs. It also meant a dramatic change in how the project would be managed, and added complexity to coordinating development schedules between the two design teams. And for both teams, this changed everything. The design teams, one based in Palo Alto, Calif., and the other in Colorado Springs, Colo., created a new converter package that leveraged a previous A/D converter design used successfully in Agilent's mid-range digital oscilloscopes. For example, the latest design combines 80 A/D converters, all time-interleaved on a single chip. Previously, the most combined was 32 converters. The company says that no other gigasample A/D converter design has used more than six. I talked with Brian Setterberg, a member of the elite Agilent Labs, and he told me that his group was looking to make the most energy-efficient design they could, at whatever speed they could get out of it. The first step was to interleave as many of the converters as possible to get the highest aggregate sample rate. Brian said that was a big mental shift. Looking at the block diagram, you notice that the team interleaved 80 different pipeline converters to get the highest aggregate sample rate. That is quiet a departure from what designers normally do. Traditionally, there would be interleaving by a factor of two, and maybe, if the designers were aggressive, they would interleave up to four converters. Agilent took that to the extreme with 80 converters. click for full-size image Adding more converters also had the undesirable effect of reducing bandwidth. To counter this, an input-buffer chip was added to increase the bandwidth to six times greater than in the previous CMOS A/D converter design. And while this was accomplished using the more expensive silicon germanium (SiGe) semiconductor process, the cost impact of this small chip to the overall package was minimal. Another significant challenge for the Agilent Labs' team included redesigning the new chip so that it used only half the supply voltage of the previous design—down to 1.6 V from 3.3 V. This enabled the team to embed system memory on the chip and improve performance. Other challenges included trying to match the 80 converters. "Obviously, the 80 converters had to match," Setterberg said. "Any offset differences between them and the design wouldn't work." Agilent got the timing adjustment for each of the A/D converters to within 0.2 ps. The converters operate in a reduced-radix mode. That means that rather than being a binary radix where each stage has a gain of two, Agilent reduced the radix to a gain of 1.6. That gave them redundant code so it can account for comparator offsets, and amplifier gain and offset errors. The block labeled radix converters converts the radix and takes care of some of the fine tuning or impairments that might be there. Then there's the on-chip memory. Its job is to handle the full 160 data bits per second. It provides a buffer and solves the problem of how to get the data off the chip. Toward the front end of the block diagram are the 80 track-and-hold (T/H), which are timed precisely. Additionally, since there are 80 different converters on the chip, the input capacitance is high and must be controlled. Setterberg alluded to the fact that the design relies heavily on calibration to make it work. It turns out that scopes have calibration sources built into them for calibrating the channels and the probes. The team took advantage of those to help calibrate the chips. There's also a PC motherboard in the scope with a Pentium processor, and we can use that for computing calibration coefficients and upload them into the converter chip. I asked Brian if Agilent had any plans to use this concurrent-design concept, having the designers of the chips work alongside the designers of the equipment for other products. He said, not giving anything away, that it's hard to say—but at Agilent Labs we tend to do a lot projects for key technology that have a lot of risk. It's generally not possible to do it for every design. In this case, we had proof from a previous design that it worked, and that helped give us confidence that we could pull this off.

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