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M•CORE Architecture implements Real-Time Debug Port based on Nexus Consortium Specification

By David Ruimy Gonzales
Senior Member of Technical Staff
M•CORE Technology Center

Real-time embedded microcontrollers introduce new challenges to designers as they become more highly integrated. Most embedded controllers execute code from internal memory and provide little to no visibility of how programs flow. Prior techniques for providing visibility of deeply pipelined instruction execution units have cost performance hits as well as increased pin count. Because each silicon vendor may choose different tradeoffs between performance and visibility, it is very difficult for tool vendors to produce tools that offer consistent functionality across architectures.

A consortium of competing companies has developed a specification which describes a standard for developing highly embedded microprocessor applications. Originally started by five founding companies (Motorola, Siemens, Hitachi, Etas and Hewlett Packard), there are now twenty companies participating in this consortium. Officially named the Global Embedded Processor Debug Interface Standard (GEPDIS) the project has been code named Nexus.

The objective of the consortium is to define a common set of microcontroller on-chip debug features, protocols, pins and interfaces to external tools which may be used by real-time embedded application developers. The consortium has been organized into four committees which address business issues, the technical specification, software and validation. At this time the Nexus Consortium has finalizing revision 1.0 of the specification and is currently working on the IEEE standardization process. The specification has been handed over to the IEEE Industry Standards and Technology Organization (IEEE-ISTO) as of September 23,1999.

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