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Rapid development of embedded applications in short time frames has generated a market for reusable micro-RISC architectures. These cores are being offered in two forms, custom gate level macrocells and fully synthesizable RTL models. Custom gate level macrocells are ideal for lower power and smaller die size but are not easily retargetable to different fabrication technologies without a new cell library. Synthesizable RTL models are ideal for rapid deployment to different fabrication sites and provide a rapid prototyping path using FPGAs but have larger die size, consume more power and may not work at the same speeds as custom macrocells. In both cases there is a list of important items to the bill of materials which comprise a complete product development cycle when designing with a reusable micro-RISC core.

Design teams who need a popular microcontroller architecture which fits their price, power, performance and support requirements will be looking for a complete solution to their product development plan. This includes access to libraries of special peripherals, circuits and device drivers, well-defined bus interfaces, a well-supported suite of software and hardware co-simulation tools and rapid prototyping capability using FPGAs.

The focus of this paper is to describe the M-CORE M210S fully-synthesizable core architecture, its design methodology and development tools which support rapid prototyping for wireless, consumer and automotive applications. An architectural overview of the M210S will include the programmer's model, a hardware local bus interface and a peripheral bus interface standard. Emphasis will be placed on tools which assist in transitioning from a hardware description language (HDL) modeling environment to a rapid prototyping platform using FPGAs.

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