Overview

Motorola's M•CORE Technology Center has developed a new embedded microcontroller specially designed for low-power portable applications. The microcontroller implements an M•CORE integer processor with 256 K bytes of on-chip ROM and 32 K bytes of SRAM with battery backup support. It operates off an internal 2-V supply while its peripherals interface to 3.3-V components. This mix of low-power computing and easy interface to industry-standard components provides a means for designers to quickly develop real-time portable applications.

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The MMC2001 provides a select set of peripherals consisting of a timer/reset module, an asynchronous serial communication port with infra-red detector support, a 16-bit general-purpose I/O port with keyboard scan/encoder capability, an 8-bit general-purpose I/O port with support for edge-/level-sensitive external interrupts, and a six-channel pulse width modulator. This combination of peripherals, processor and memory provide an optimal mix of resources for addressing a number of embedded applications requiring long battery life: Portable instrumentation for measuring seismic activity, unmanned aerial controllers, remote data-gathering devices which communicate with host computers via infra-red, PDAs, or a number of telecommunication devices.

Instruction Set Efficiency Reduces Power

The microprocessor uses a streamlined execution engine that provides many of the same performance enhancements as mainstream RISC architectures. It's a fully-static CMOS M•CORE architecture that packs about 80,000 transistors in a 2.2-mm2 square of silicon in a 0.36-micron process. The architecture implements logic within portions of the core execution and control blocks to minimize power and reduce EMI. In addition to providing mechanisms to power down the processor and system logic, there is focus on minimizing dynamic power consumption when the system is active.

Optimal instruction set efficiency is accomplished in the M•CORE architecture by implementation of a universal load-store RISC engine. It is implemented with a fixed 16-bit instruction and a 32-bit internal data path which meets the computational precision requirements of newer advanced products, with the cost and power advantages previously available only with 16-bit architectures. So, increased code density accomplishes the goal of minimizing the overhead of memory system energy consumption.

The core contains a 16-entry, 32-bit general-purpose register file, and processes instructions using an efficient four-stage execution pipeline. All computational activity takes place within the internal registers, thus reducing external bus transients that would consume power. The arithmetic unit contains a barrel shifter providing fast-multiply and signed or unsigned divides of integers, as well as special help in the translation of incoming/outgoing data, such as single-cycle bit-reversal of a 32-bit word. Data movement is accomplished using load/stores of single or multiple registers in one instruction. This facilitates fast and efficient register use when entering/exiting subroutines and context switches between user and supervisor modes.

Power-Saving Operating Modes

To provide optimal static-power management for the overall system, the M•CORE architecture provides three instructions (stop, wait, and doze) that disables power to pieces of the system. Computationally-intensive algorithms are executed in normal mode and asynchronous external events, or time of day occurrences, can be dealt with in either a doze, wait or stop mode. In each of these modes the user has the option of enabling or disabling peripheral clocks, so optimal power savings may be accomplished when waiting for an event to occur.

Power-Aware Instruction Pipeline

The M•CORE architecture optimizes dynamic power consumption by both minimizing the power needed to execute an instruction and minimizing the number of bytes that need to be fetched to perform a given function. The M•CORE architecture achieves this benefit through its power-aware pipeline. The instruction pipeline recognizes which processor functions are required to execute a particular instruction, enabling it to ensure that data only transitions through the processor blocks that are actually needed to implement the instruction. For example, an add instruction would cause data to transition through the adder but not the barrel shifter. By eliminating unnecessary transitions the architecture prevents switching of gates, loads, and wires in unused blocks, all of which would otherwise consume additional power.

Timers Help Reduce Power

A timer/reset module is made available to help reduce power. This module consists of three independent timer blocks, the chip-reset control and the battery-backup control logic for the on-chip SRAM and one of the three timers. The three timers are for time-of-day (TOD), for periodic intervals (PIT) and as watch dog (WDT.) They are all clocked by a low-frequency 32-kHz single-inverter oscillator with an 8-bit prescaler, which provides three separate frequencies: 256 Hz to the TOD, 8 kHz to the PIT and 2 Hz to the WDT.

The TOD's real-time clock functionality is with an 8-bit fraction register that counts to zero and increments a 32-bit seconds counter. The TOD is tied to the battery backup control logic.

When enabled the 6-bit WDT provides a means for safeguarding the system, forcing the application to write a sequence to the timer before it decrements to zero, or a chip reset is asserted. After the sequence is written the WDT is reloaded with its 6-bit value and restarts the countdown. This technique is frequently used in noisy or harsh environments.

Also. power-on-reset (POR) logic is built on-chip so that clocks fed to on-chip resources are not enabled until the 32-kHz oscillator is stable, and the program controller is functional. This reduces battery drain on power-up.

Interrupt Handling

A feature of the MMC2001 is its ability to efficiently service real-time interrupts with as many as 32 sources being serviced in two categories: Normal or fast. A special port may be programmed as a general-purpose I/O or as an individual interrupt. These inputs may be programmed as edge-triggered, sensitive to either rising, falling or both edges as well as being level-sensitive. Each interrupt may be independently enabled/disabled and may be programmed as fast or normal types. An interrupt register provides a means for determining which inputs caused an exception and the register facilitates handling multiple simultaneous interrupt exceptions.

Pulse Width Modulator

A six-channel PWM, which has a programmable time period as well a as programmable duty cycle, allows for an interface to audio or motor-control applications. The width and pulse registers are double-buffered so that a new value can be loaded without disturbing the current cycle. It has periodic interrupt capability and the pins can be configured for general-purpose I/O when they are not used as PWM channels. A doze bit in the PWM control register allows the module to be disabled and put in a low-power mode whenever the processor is in the wait or doze mode -- so that battery life may be conserved.

Reducing External Memory Accesses Saves Power

Although the architecture is 32-bits, the processor uses a 16-bit instruction set to achieve high code density. This 16-bit instruction set provides a performance advantage over conventional RISC architectures in many low-cost applications. It is common for such applications to minimize cost through the use of a 16-bit bus. Since RISC architectures use 32-bit wide instructions they have to perform two bus cycles to fetch an instruction, negatively impacting overall instruction throughput. In contrast, the M•CORE architecture requires a single bus cycle to perform an instruction fetch, enabling it to run at full speed even with a 16-bit bus.

To further minimize bus activity, the architecture reduces the need to read and write data to and from memory, by providing a set of registers that enable a program to keep data variables in memory while they are live. The architecture provides a total of 37 32-bit data registers that are available to system programmers, one set of 16 general-purpose registers, an alternate register file with 16 registers, and 5 scratch registers.

Some commonly used data types such as chars or shorts have 8- or 16-bit, rather than 32-bit,representations. This provides an additional opportunity for the M•CORE architecture to reduce power consumption when fetching data from memory toggling, for example, the 8 bits required to read or write a char, minimizing power consumption by logic external to the processor core.

The MMC2001 provides an external interface module with 4 chip-select signals, a programmable wait-state generator, 20 address lines and a 16-bit data bus that provide an efficient external memory or peripheral interface with minimal external glue logic requirements. Booting out of reset may be either through internal or external ROM and transfer size control pins allow for efficient byte, half-word or word memory accesses.

Application Development Environment

The MMC2001 is complemented by an extensive set of third-party development tools, turn-key hardware evaluation boards, and on-chip emulation support for quick evaluation and custom application development. To accelerate system level integration and to also provide a means for production and field testing of new product, a Motorola-standard OnCE block is available on the processor. This provides a dedicated emulation interface for rapid evaluation of the system hardware and software. Communication with the block is conducted via a 5-wire IEEE-1149 JTAG controller and provides direct access to each of the processor's instruction registers so opcodes may be fed directly to the instruction pipeline, bypassing external accesses to memory. This mechanism provides a true non-intrusive means for controlling the processor directly in the target system.

Software and hardware breakpoint registers are provided along with a FIFO program counter-trace buffer which stores change of flow addresses. Single-stepping opcodes with a 16 bit counter is available and the OnCE registers are accessible while the core runs in real-time or is in reset. This interface is useful for measuring static and dynamic power consumption and also allows analysis of code hot spots.

The JTAG/ OnCE interface is currently supported by an Agilent (HP) processor probe which communicates with a software development system (SDS) source-level debugger. C/C++, as well as assembly-language programs compiled using a Diab Data M•CORE architecture cross-compiler can quickly be evaluated in this environment.

System level hardware/software co-verification tools are available from Summit Design and allow source-level debugging within a Verilog simulation environment. This allows designers to debug FPGA circuits described in an HDL language using the control software written in C or C++.

Summary

As handheld battery-operated devices evolve at lightning speed, the issue of high performance with low-power consumption will present new challenges to portable product designers. In order to design these new products in a timely manner a complete solution is of utmost importance for rapid delivery. Motorola's new MMC2001 M•CORE based processor provides the low-power architecture, advanced tools and technical support to solve these new challenges. The M•CORE architecture is recognized as a strategic corporate program within the company to provide a path for flexible yet re-usable technology for current and future designs.

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