IBMıs ASIC product offerings include components with very large numbers of I/Os. Conventional through-the-pine test methods are very expensive; each high-speed tester channel may cost $10,000 or more. To control tester capital investment costs while maintaining test quality, IBM has chosen to connect only a subset (currently 64) of signal I/Os to high-speed tester channels for testing each ASIC component. This subset of signals I/Os provides access and control of all scan elements internal to the ASIC components, including boundary-scan cells.

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