Today's Features

Cadence Introduces Incisive Verification Platform (Product of the Week)
The heart of Cadence's unified Incisive top-down verification methodology is the transaction-level-based Functional Virtual Prototype (FVP). According to the company, the creation of transaction models takes a fraction of the time required for RTL descriptions, and the transaction models run about 100 times faster. In fact, the claim is made that the Incisive system and methodology can reduce total verification effort and time by a factor of two—a truly significant reduction in project cost.

Product Reviews

Cadence Introduces Incisive Verification Platform (Product of the Week)
OpenAccess and Synopsys Working Together
IBM Pushes PowerPC Licensing

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Tech Notes

RTL Handoff by Reed Packer, AMI Semiconductor, Inc.

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Application Notes

Formal Verification of Equivalence in DSM Design by Roger Hughes, Mentor Graphics

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News

Synplicity Enhances Prototyping Tool
MMIC Design Flow from Agilent
Mentor Unveils PCI Express Controller
Rambus Describes Redwood
ARM Works With Canesta
Cadence First Encounter Selected by TI
Synopsys Announces IP for PCI Express
Lightspeed Uses Sequence for Signal Integrity
ARM and Emuzed Team on Enhanced Functionality
Silterra Standardizes on Mentor's Calibre
Circuit Semantics Joins Synopsys in-Sync Program
Synopsys Adds AMBA Compliance Tool
AMD Selects Atrenta's SpyGlass
Ansoft Announces SIMPLORER
Agere and Accelerant Deliver Technology
InnoLogic Tools Validate Models for ST
Toshiba Selects CoWare
Mentor Calibre Files Available for 90 nm at UMC
Chartered Details Strategy
Verplex Equivalence Checking For Embedded Memories
Monterey Design Deployed TeraChip
Accelerated Technology and MCCI Announce USB Support
ARM Launches AMBA Compliance Program

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