TSMC Proving 90 nm CMOS Process

Tensilica's Xtensa Core Validated

IC4IC Connects with Tensilica

Cadence Adds to SPW

TransEDA Launches Property Checker

Cadence Offers NC-Sim Plus

TransEDA Launches IP Quality Program

AXYS Design Unveils MAXSIM 2.1

Axis Systems Develops Language-Neutral Platform

JPEG2000 Core from Amphion

Tensilica Licensed by OptiX Networks

Sequence Models IP for SOC Power Design

Artisan Libraries Tapped by Centillium

Chartered and Artisan Announce Agreement

Toshiba Selects NeoCircuit

Monterey Design's Timing-Driven Top-Down Design Planner

Celestry Selected by STMicroelectronics

Plato's NanoRoute Used for Sun Servers

Tality Verifies Its Ethernet IP

NIST Approves Tality's Encryption IP

Synplicity's Strategic Relationships

Esterel Adds Capabilities to Esterel Studio

Avant!'s Astro Enables Ricoh's Tapeout

ModelSim Achieves Sign-Off Status at STMicroelectronics

Verisity Launches eCelerator

Virtual Silicon Libraries Available for PrimeTime

Nassda's Full-Chip Circuit Simulator

Chartered and Artisan Announce Agreement

Synopsys Accelerates VCS Performance

Mentor Introduces C-Bridge for Seamless

Chartered Expands Open-Library Program

Avant!'s Astro Chosen by ETRI

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