Fujitsu Deploys Cadence Timing Closure Technology

Verisity and Novas Facilitate Debug Interoperability

MoSys Announces 1T-SRAM Memory Compiler

Azanda Leverages Denali's Memory Controllers

Sonics Introduces New Interconnect IP

Telairity Adopts Circuit Semantics' Tools

Monterey Design Targets Multimillion-Gate Chips

Acer and Cadence Announce Strategic Alliance

MoSys Licenses 1T-SRAM-R Memory to Hitachi

SuperH Registers Cores on VCX

Physical Synthesis Customers Adopt Cadence's NanoRoute

ASE Establishes Cadence Design Flow

IP Flex Accelerates Development with Novas Debug

Mentor and Genesys Deliver Integrated USB 2.0 Core

TI Finds Opportunity in Big, Fast ASICs

LSI Logic's New Physical RTL Optimization Flow

Mentor Offers Model Support for ARCtangent

Samsung Selects NeoCircuit

Sanyo Standardizes on Novas Debug Software

Accelerated Technology Announces E-SIM Prototyping

Virtual Silicon Offers IP for IBM Foundry

Bay Verifies Chip with Verplex Tools

TSMC and Cadence Collaborate

Artisan Components and Cadence Team

0-In Delivers Monitors for Interface Standards

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