Cadence and TSMC Team

IBM and Cadence Use Linux

MoSys 1T-SRAM-R Memory Proven At UMC

AMD and IBM to Develop Chip Technologies

Neolinear Announces NeoCell v3.2

Mentor and UMC Strengthen Partnership

0-In Verification Products Used by National

Cadence and ATI Team

VDEC Recommends Magma Software

SiS Standardizes on Synopsys' Physical Compiler

Synopsys PrimeTime SI Enables Closure

Mentor Graphics Joins 0-In Partner Program

Virage Logic Uses InnoLogic Tools

Fujitsu Standardizes on Synopsys PrimeTime

Mentor's IP Repository Adopted by Faraday

Lambda Licenses Amphion JPEG IP

Lightspeed IP Program Launched

Aptix Unveils Verification and Prototyping Environment

Cadence Extends Leadership

TSMC's 90 nm Libraries Validated in Synopsys Flow

Mentor Announces TransEDA VN-Cover Support

Virtual Silicon and Magma Team

Synplicity's ASIC Synthesis Release

Axis Systems Introduces Entry-Level Systems

Summit Design Announces Visual Elite 3.1

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