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Summit Design Launches Sixth Generation of Visual HDL

The manufacturer says . . .

Murray Disman says . . .

Summit Design Inc., a leading supplier of high-level design automation software, today announced the release of HDL 6.0, the latest version of its state-of-the-art design environment.

Version 6.0's substantial enhancements across several major functional areas will maintain Visual HDL's position as the tool to be emulated by other developers of high-level design automation products. All new features integrated in this version are designed to further raise productivity and shorten the design cycle by adding new dimensions and work methods to the design process.

Visual HDL is now equipped with a new Waveform editor which allows the graphical definition of test vectors and cycle-based patterns for functional block verification. Version 6.0 also provides a highly efficient Macro library, designed to speed up the creation of DataPath designs using a set of configurable, technology-independent Tcl-based macros. Visual HDL users can also now run cycle-based simulation using the Cyclone engine.

"The new Code Style Manager introduced in this version enables high-level control of the generation of output code from different design blocks, as well as the multifaceted customization of style checking and design rules," said Rami Rachamim, director of visual marketing. "Visual HDL now supports a wide range of tools and formats which can be used for documentation purposes such as OLE for Microsoft Office, MIF for FrameMaker, and hyperlinked HTML generated from complete design hierarchies."

Price and Availability

Visual HDL 6.0 is now available with the following simulation engines: Visual HDL, ModelSim, Leapfrog, VSS, SpeedWave, Cyclone, Verilog-XL, VCS and Polaris. On UNIX, it runs on SunOS and Solaris, HP-UX, and IBM-AIX; and on PCs under Windows 98 and Windows NT. Starting price for a node locked license is US $15,000.

Visual HDL has proven to be a valuable productivity tool as it provides designers with a variety of graphical, tabular, and textual editors to capture and verify structures and design blocks. Block diagrams, state diagrams, flowcharts, and truth tables are used to capture functional blocks, algorithmic behavior, control logic, datapath, and other logic structures. The tool can also read existing HDL text, create block diagrams for HDL code, or automatically generate HDL code from a graphical representation. The additions provided in version 6.0 will further enhance Visual HDL as an aid in increasing designer productivity.

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