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Verisity Adds Dual-Language Support

Verisity's Specman Elite Adds Dual-Language Support for Cadence's Affirma NC Simulator

The manufacturer says . . .

Murray Disman says . . .

Verisity Ltd., the leading provider of functional verification automation solutions, today announced that Specman Elite, the company's testbench automation product, supports the Cadence Affirma NC simulator for both VHDL and Verilog hardware description languages. Customer demand for VHDL fueled Verisity, a member of the Cadence Alanza Group Connections third- party software program, to increase its support for VHDL simulation solutions. In June 1999, Verisity announced support for the Affirma NC Verilog simulator and now supports the Affirma NC VHDL simulator, as well.

"VHDL is the dominant design language for customers in the communications sector and in Europe in general," said Peter Hwang, director of marketing at Verisity. "Our decision to support the Affirma NC simulator for VHDL was driven by our market leadership in these high growth segments. The Affirma simulator is an industry-leading simulator and the integration enhances our language-neutral solution."

As systems-on-chip designs continue to proliferate, engineers are working more often with both languages. Often engineers design an ASIC or system in either VHDL or Verilog and import intellectual property (IP) created in the other language. Verisity's language-neutral functional verification solution enables users to import any intellectual property (IP), regardless of the language it was created in, and effectively verify the IP in the context of the entire system.

"We are committed to supporting our mutual customers with best-in-class solutions," said Jeff Nathan, product marketing manager at Cadence Design Systems, Inc. "The Affirma NC simulator is, by far, the highest performance mixed-language simulator on the market. By integrating Affirma NC simulator with Specman Elite, we are providing our mutual customers an integrated solution for verification of Verilog, VHDL or mixed-language designs."

Availability and Support

Verisity's Specman Elite 3.2 with language-neutral support of VHDL and Verilog is available immediately. Specman Elite 3.2 currently supports the following simulators: the Verilog-XL simulator, the Affirma family of simulators (NC sim, NC Verilog, and NC VHDL) and the Leapfrog simulator from Cadence; the SpeedSim cycle-based simulator from Quickturn (a company of Cadence Design Systems); ModelSim from Model Technology and VCS from Synopsys.

Although the majority of ASIC designers in the U. S. use and prefer Verilog, VHDL is becoming a viable alternative language in a number of situations. VHDL is actually the preferred design language in Europe because of its adoption by local standards organizations. The language is also gaining popularity in certain sectors of the industry in the United States. In addition, new engineers have usually been trained in the use of VHDL at school.

Prototyping of large designs in FPGAs is a practice that is becoming commonplace in the ASIC development process. Many of the FPGA designers, IP cores, and tools use VHDL. Verisity's capability of producing verification test benches in both Verilog and VHDL is an important addition to the designers toolkit.

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