ARM Introduces ARMv6

The manufacturer says . . .

Murray Disman says . . .

ARM Announces Technical Details of Next-Generation Architecture New ARMv6 Architecture Raises Performance Levels to New Level of Embedded Processing CAMBRIDGE, U.K.--Oct. 17, 2001--ARM, the industry's leading provider of 16/32-bit embedded RISC microprocessor solutions, announced that it has extended its microprocessor-technology road map with the introduction of the next-generation ARMv6 architecture. ARM gave a presentation at the Microprocessor Forum in San Jose, Calif., disclosing the technical details of this new ARM architecture. The ARMv6 architecture has been developed by working closely with our architectural licensees such as Intel Corporation and Motorola, and our year-long collaboration with Texas Instruments Incorporated, to extend the capability of the ARM architecture while maintaining code compatibility with earlier ARM core-based products, thereby safeguarding Partners' investment in software. The ARMv6 architecture adds the Single Instruction, Multiple Data (SIMD) instructions, as announced last year, to the proven ARM ISA, boosting performance in audio and video functions by as much as four times. Further enhancements that are part of the ARMv6 architecture include an enhanced level-one memory system as well as improved data synchronization and shared memory management for the efficient implementation of multi-processor systems. "The complexity of embedded systems is growing rapidly, and the development of the ARMv6 architecture will enable our Partners to significantly increase the capability of their platform and embedded solutions in a wide variety of applications," said John Rayfield, director of R&D, ARM. "The ARMv6 architecture includes innovations in the level-one memory system design to boost system performance significantly. Additionally, the new capabilities in the areas of data sharing and synchronization will increase the performance of multiprocessor systems." Benefits of the ARMv6 Architecture 30 percent increase in system performance—With the addition of an enhanced level-one memory system, which includes features such as a tightly coupled Direct Memory Access (DMA) controller and re-architected cache, the overall system performance is increased on the ARMv6 architecture by as much as a 30 percent. Better multiprocessor support—As a result of a year-long collaboration with Texas Instruments, the ARMv6 architecture includes enhancements to data synchronization and shared memory management. These improvements have a significant impact in applications such as 2.5 and 3G wireless platforms where there is a common need for ARM processors to interact with DSPs and other application accelerators. Application convergence—The ARMv6 architecture provides improved mixed-endian support and unaligned data in hardware. This enables developers to handle bi-endian systems seamlessly, an important benefit as highly connected applications with different endian requirements converge. Up to 8× performance increase for media applications—In addition to the SIMD capabilities, which will boost the performance of media applications such as audio and video encoder/decoders by up to four times, the ARMv6 architecture also includes enhanced instruction-set support for motion estimation. This new capability will increase the performance of video encoders by a factor of at least two, enabling developers to make a significant saving in power when implementing these functions. Availability The ARMv6 architecture will be incorporated into the next generation of ARM microprocessor cores scheduled for delivery in 2002. The cores can be licensed as intellectual property (IP) for implementation within application-specific integrated circuit (ASIC) or application-specific standard product (ASSP) designs.

Customer requirements for more complex applications have led ARM to its next-generation architecture with increased performance and facilities to aid in multi-processor and multimedia applications. The addition of new instructions, while maintaining code compatibility with earlier ARM processors, and a redesign of the memory sub-system were the primary changes made. The memory improvements include closer coupling between the processor and the L1 cache, an increase in memory bandwidth by adding to the DMA capability, and shared memory management enhancement for multi-processor systems. These were all implemented to reduce the processor's memory activity, increase the efficiency and speed of processor-to-memory access, and reduce latency.

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