Synopsys Delivers SystemC Simulator

The manufacturer says . . .

Murray Disman says . . .

Synopsys Delivers Commercial SystemC Simulator CoCentric System Studio completes Synopsys' SystemC design and verification solution. MOUNTAIN VIEW, Calif.--Feb. 11, 2002--Synopsys, Inc., the technology leader for complex integrated circuit design, introduced a commercial SystemC simulator, completing its SystemC design and verification solution with its latest CoCentric System Studio release. System Studio now supports the joint verification and analysis of algorithms, architectures, hardware, and software, accelerating the development of competitive systems-on-chips (SoCs). System Studio vastly simplifies the system-level SoC design flow by offering one simulator that spans from concept to implementation in hardware and software. The combination of CoCentric System Studio and CoCentric SystemC Compiler, Synopsys' SystemC synthesis product, provides the most advanced SystemC design and verification solution available today. "Design of very complex chips is moving to the transaction level in SystemC, with RT-level detail added for synthesis once the design team has closed on the architecture," said John Chilton, senior vice president and general manager for the IP and Systems Group at Synopsys. "With our new SystemC simulator, combined with our existing SystemC synthesis product, we provide designers with the essential tools for this new design paradigm. With this announcement, SystemC-based design is here." While Hardware Description Language (HDL)-based Register Transfer Level (RTL) verification remains critical for detailed hardware design, it is not sufficient for system-level SoC design. System Studio's SystemC simulator enables designers to verify complex SoCs with multiple processors, buses, and peripherals earlier in the design cycle. The simulator allows designers to simulate hardware and software interaction at higher levels of abstraction than traditional RTL, resulting in an orders-of-magnitude simulation speed-up. Finally, System Studio's flexibility to mix different abstraction levels using a single language enables designers to optimize the design and verification flow for SoC projects. Early Embedded Software Development and Verification Verifying the real-time interaction of hardware and software in the application environment is a critical step to ensure the products being designed are functioning correctly. Unfortunately, the current hardware/software co-verification approaches attack the problem too late in the design cycle. They require a fully detailed RTL HDL description of the hardware, making the verification of embedded software inherently slow. In addition, if major design flaws are discovered at this stage, it is usually too late to recover. The solution is to create a system-level hardware representation that simulates quickly and can be used to run and debug embedded software early in the design cycle. "We validated a SystemC-based design flow with Synopsys and found advantages to modeling, verification, and analysis in the early design stages of SoC development," said Kazu Yamada, general manager, NEC Electronics, Inc. "We designed and simulated MPEG components from algorithm to behavioral SystemC for the architecture tradeoff and embedded software debugging. CoCentric System Studio helped us describe, execute and analyze the whole system easily and efficiently." Enabling System-Level Verification In the past, due to the lack of a standard system-level design language, design teams resorted to proprietary extensions of C and C++ for their system-level verification efforts. As a consequence, it was difficult to use other design team's models. "ST has been doing C-based system-level design for many years, and we have amassed a significant portfolio of C-based simulation models of our design blocks. We were able to very quickly adapt our C-based transaction-level models to SystemC, and are using them in CoCentric System Studio for system-level verification of our complex designs," said Philippe Magarshack, Central R&D group vice president and CAD director, STMicroelectronics. "With the availability of SystemC, designers are now able to create reusable system-level models of design blocks that can be shared across teams, projects, and companies." LSI Logic Corp., a leading provider of complex multi-processor based SoC solutions, has been evaluating CoCentric System Studio for use in developing next-generation multi-processor platforms incorporating ARM, MIPS, and ZSP processors for high-end communications, storage, and consumer applications. "CoCentric System Studio helps us to manage the complexity of capturing, simulating, and debugging for SystemC designs," said Steve Emerson, manager of Advanced Systems and Platforms, LSI Logic. "SystemC provides a promising approach to model and perform system analysis of processor-based systems. The use of SystemC is especially interesting because it is an open standard and has the potential to enable the use of a single language to perform modeling, system analysis, design capture, and testbench creation." Synopsys' Verification Solution CoCentric System Studio is part of Synopsys' complete line of functional verification solutions supporting SystemC, Verilog, VHDL, mixed-HDL, and mixed-signal simulation for complex SoC designs. These solutions, aimed at achieving the highest verification productivity, include Synopsys' VCS Verilog simulator, Scirocco VHDL simulator, the MX package for mixed-HDL simulation, the VERA testbench automation tool, the VCS-NanoSim package for mixed-signal simulation, and the Formality equivalence checker. Pricing and Availability CoCentric System Studio 2002.05 will ship in May, 2002. Pricing for CoCentric System Studio starts at US$ 26,950 for a one-year technology subscription license (TSL). Customers with current maintenance agreements will receive the release at no additional cost.

According to Synopsys, the 2002.05 release of the SystemC simulator completes its SystemC design and verification solution. The main elements of the design flow are CoCentric System Studio for simulation, and CoCentric System SystemC Compiler for synthesis. CoCentric System Studio grew out of COSAP, the company's DSP design and simulation tool. Synopsys seems pleased with the acceptance and growth of SystemC, an effort it initiated in 1999. It claims that there are 15,000 registered licenses and that there have been about 2,000 downloads of SystemC v2.0. System Studio was introduced by Synopsys to provide a robust simulator with HDL co-simulation, design entry, and source-code debugging. The free SystemC simulator, which is available from the Open SystemC Initiative, was described as being limited in capability and difficult to use. The System Studio simulation environment, which is to be released in May, 2002, has been in beta at four sites since October. The number of beta sites was increased to 24 in December. Important claims for System Studio are that it enables verification at multiple levels of abstraction, and also enables hardware/software co-simulation at an early stage in the design process. According to the company, execution of the processor software can be simulated using a transaction-level or pin-level model of the processor. System Studio supports both graphical and text design entry. It has an API-based co-simulation capability with the company's VCS Verilog and Scirocco VHDL simulators. The company plans to provide a direct kernel interface to improve the co-simulation speed. Synthesis to either FPGA or ASIC netlists from the SystemC code is accomplished by using CoCentric SystemC Compiler in conjunction with either FPGA Compiler II, Design Compiler, or Physical Compiler. SystemC Compiler uses Synopsys' behavioral synthesis technology, from Behavioral Compiler, for automatic scheduling and resource allocation, memory inferencing, automatic loop pipelining, behavioral retiming, and control FSM generation. While the new simulator can work with descriptions and models in C/C++, input to the compiler must be from the SystemC C++ class library.

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