Mentor Introduces SpeedGate

The manufacturer says . . .

Murray Disman says . . .

Mentor Graphics Introduces SpeedGate Direct System Verification Environment for Rapid ASIC Prototyping WILSONVILLE, Ore.--Feb. 18, 2002--Mentor Graphics Corporation introduced SpeedGate DSV (Direct System Verification), an advanced verification environment for creating application specific integrated circuits (ASIC) and System-on-a-Chip (SoC) prototypes using off-the-shelf field programmable gate arrays (FPGAs). Silicon prototypes created by SpeedGate DSV can be tested at speeds comparable to a real-time operating environment, significantly reducing costly, time-consuming silicon respins. SpeedGate DSV adds a mid-priced ASIC verification technology to the industry 's most complete verification flow that encompasses solutions from logic simulation to co-verification. Today, ASIC verification consumes 30 to 70 percent of total ASIC design time. With costs for a 0.18 µm ASIC mask set exceeding $500,000, the financial impact of a silicon re-spin is substantial. Persistent budgetary and time-to-market pressures require a solution that reduces the verification cycle while maintaining a high level of accuracy. SpeedGate DSV addresses all the hardware prototype creation and verification challenges from partitioning, debug, and interconnect to rapid board creation and analysis. By leveraging advances in commercially available FPGA technologies, SpeedGate DSV duplicates an ASIC design in an in-circuit environment. SpeedGate DSV provides in-circuit verification in a moderately priced solution, running three to four orders of magnitude faster than low-end tools. "SpeedGate DSV provides one of the most sophisticated and robust environments for partitioning and debugging ASIC and SoC prototypes," according to Rich Sevcik, senior vice president and general manager, Xilinx, Inc. "Designers porting to our Virtex FPGAs using SpeedGate will find the most accurate representation of their designs in a cost-effective prototype." "The versatility of SpeedGate DSV makes it a perfect complement to any existing verification flow," said Anne Sanquini, vice president and general manager of the HDL Design Division of Mentor Graphics. "For advanced flows making use of high-end emulation tools, SpeedGate DSV can be used to create low-cost ASIC replicates that can be passed to software engineers for rapid system debug. For cost-constrained methodologies, SpeedGate DSV delivers close to at-speed system verification at orders of magnitude faster than low-end solutions." About SpeedGate DSV SpeedGate DSV is the most comprehensive and extensible solution for all aspects for the prototype design flow—partitioning, debug, and interconnect. It also links to board creation and analysis tools. An interactive design cockpit launches partitioning and synthesis tools, and the completely scriptable interface plugs into any ASIC design environment—working hand-in-hand with emulation and gate-level simulation. SpeedGate DSV includes a patent-pending advanced partitioning technology that enables designers to minimize the number of FPGAs used to prototype a design. SpeedGate DSV fully supports the prototyping process with a team design environment, including sophisticated check-in/check-out features that track source code changes and manage version control. Pricing and Availability SpeedGate DSV is available now at a price of $98,500 for a floating license. SpeedGate DSV supports Sun Solaris 2.7 and 2.8, and supports ASIC partitioning on Xilinx Virtex FPGAs.

While the EDA companies are developing software-based virtual prototyping schemes, the "real designers" are already working with FPGA-based hardware prototypes. Hardware prototyping of ASIC designs has been going on for years. Software-based virtual prototyping systems are just coming on-scene, and are typified by Synopsys' SystemC-based CoCentric System Studio. The goals of both approaches are to speed the verification process and provide a platform for software development and co-verification. Software-based virtual prototyping systems use high-level languages and rely on models of hardware modules, processes, and processors. While the speed of the software-based virtual prototyping systems is substantially higher than traditional simulation schemes, the hardware-based prototypes can operate much faster, often approaching system speeds. The advantages of the virtual prototyping systems are flexibility and ease of debugging. Their disadvantages are speed and the accuracy/completeness of the models used. Hardware-based prototypes can be difficult to debug and to partition into the multiple FPGAs required for the ASIC design. The primary partitioning problem is that of choosing the partitions so that the number of resulting I/O connections is less than the number of I/Os provided by the FPGAs. This problem is sometimes resolved by using a single FPGA pin for several partition connections. Mentor Graphic's SpeedGate DSV environment is the second system aimed directly at implementing FPGA-based ASIC prototype boards. The first system was Synplicity's Certify software that was introduced in May, 1999. Both tools carry similar prices—$115,000 for Certify and $98,500 for SpeedGate DSV. The end goal of the partitioning process is to create a board-based prototype of the design. Here the designer will have to choose either a standard fixed-routed or reconfigurable board or a custom board. Custom boards deliver the fastest system speeds, but can be time-consuming to create. SpeedGate supports all these types of boards and contains links to Mentor's board creation tools. Synplicity has a Partners in Prototyping (PIP) program that includes standard board manufacturers and design companies. The company will be announcing tighter links to its PIP partners and will integrate the software files for some of the more popular boards. Both companies have included automated techniques aimed at solving the I/O count problem by making an FPGA I/O pin perform the function of multiple pins. SpeedGate DSV's I/O Management tool provides a wrapper feature that automatically creates logic to allow specific pins to handle multiple signals as defined by the user. Synplicity's Certify pin-multiplier (CPM) feature allows a designer to use one I/O pin to transmit multiple signals between devices. According to the company, the CPM feature can be used to multiplex the I/Os with little knowledge of the target FPGA architecture.

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