CoWare Announces Interface Synthesis

The manufacturer says . . .

Murray Disman says . . .

CoWare Announces Breakthrough in Complex SoC DesignBus Architecting with Second-Generation Interface Synthesis Now Available SANTA CLARA, Calif./PARIS, France--Mar. 5, 2002--CoWare, Inc., has enhanced its CoWare N2C design system with second-generation Interface Synthesis capabilities, enabling designers to develop optimal architectures for the latest complex SoC (system-on-a-chip) designs. These capabilities solve one of the most difficult problems in today's designs—finding the bus architecture that gives the best trade-off of high performance and low power. This design decision has a huge impact on the end product, but the latest generation of SoC buses allows so many possibilities that designers can only take their best guess at the optimal architecture. CoWare N2C removes the guesswork in making these trade-offs and implementing the designs. This capability has been proven in production designs using the AMBA 2.0 on-chip interconnect and STMicroelectronic's STBus. "Many of our new SoC designs use the advanced features available in the STBus," stated Jean-Marc Chateau, Director of Design, Consumer & Microcontroller Groups, STMicroelectronics. "We worked with CoWare to enhance CoWare N2C to easily build platform variants exploiting these advanced features. We've found that different architectures can make a tremendous difference in power and performance in the end products, up to a 50 percent difference in performance in one case." In addition, CoWare worked closely with ARM to develop this new technology for STMicroelectronics and other ARM Partners. "As more designers take advantage of the flexibility and ease of implementation that AMBA technology offers, they need to be able to explore the wide range of design possibilities open to them," stated Jonathan Morris, ARM's System Infrastructure Program Manager. "Now, with CoWare N2C, our mutual customers can efficiently test different AMBA technology-based architectures to find the optimal trade-off of performance and power for their latest portable consumer devices." Today's leading interconnect solutions allow many architectural alternatives to be explored, but this carries a significant simulation overhead for the manual RTL designer. CoWare's unique design system provides the tools and methodology to model, synthesize, and evaluate different bus architectures quickly. How It Works SoC designers are now finding that complex interconnect architectures must be simulated and analyzed with sufficient accuracy before committing to an implementation. CoWare N2C allows designers to build an accurate simulation model for different configurations very quickly. The architect specifies graphically which bus masters connect to which bus slaves via which node. Each node produces a distinct bus or bus layer. CoWare's new second-generation Interface Synthesis technology, configured by this high-level input, automatically synthesizes the bus interconnect matrixes and crossbar switches, which are at the heart of these multi-layer buses. The necessary arbitration logic for multiple bus masters, along with all other bus logic, is also synthesized. Following simulation, CoWare N2C's powerful analysis tools let designers check the performance of different configurations. To change from one bus configuration to another, the designer simply adjusts the high-level input and re-synthesizes. Once the optimal bus architecture is established, the hardware design can be validated and implemented in an RTL-based design flow. This significantly speeds the hardware design process. Availability CoWare's second-generation Interface Synthesis technology has already been deployed in production designs, and is now in limited release to a select group of leading systems and semiconductor houses for designs using AMBA on-chip interconnect or STBus.

CoWare, one of the founders of the SystemC effort, is best known for its N2C system-level design tool. According to the company, the N2C design system enables designers to capture an executable and implementable system specification in C/C++, evaluate the effects of using alternative architectures, and implement and verify application-specific hardware and embedded software. N2C therefore allows designers to quickly build an accurate simulation model for different configurations. The company's claim is that by creating a detailed system specification and testing the software and hardware against that specification throughout the design process, designers can avoid unpleasant surprises at the end of the design cycle as well as significantly reduce their design-cycle time. CoWare considers its Interface Synthesis feature as the enabling technology for platform-based design. This feature also applies to software development as it automatically generates the memory map for registers and the software drivers to communicate between the software and hardware. The designer starts by selecting a base platform and then assigning functional blocks to either hardware or software. Abstract communications protocols for each block are then chosen. The Interface Synthesis feature is then used to synthesize the interfaces between the hardware modules and other hardware and software elements. This process elaborates the abstract protocols into the full detailed bus protocol for the selected processor and bus. Interface Synthesis has now been extended to synthesize the bus interconnect matrixes and crossbar switches automatically. This occurs after the system designer specifies which bus masters connect to which bus slaves via which node. Each node produces a distinct bus or bus layer. The necessary arbitration logic for multiple bus masters, along with all other bus logic, is also synthesized.

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