Cadence Announces SoC Encounter Customers

The manufacturer says . . .

Murray Disman says . . .

Major Cadence Customers Adopt New SoC Encounter for 0.13 µm Hierarchical IC Design Cadence Delivers 30-Million-Gate Synthesis/Place-and-Route Capability PARIS, France-- Mar. 5, 2002--Cadence Design Systems, Inc., introduced two new products for 0.13 µm and beyond integrated circuit (IC) design, and announced three customer design wins. The new products, Cadence® SoC Encounter and Cadence First Encounter® Ultra, integrate the Cadence SP&R (synthesis/place-and-route) solution with new advanced capabilities and technology from the Silicon Perspective Corporation (SPC), which was acquired by Cadence in December, 2001. Cadence SoC Encounter is a complete front-to-back hierarchical IC implementation solution for large-scale system-on-a-chip (SoC) design up to 30 million gates. Cadence First Encounter Ultra provides virtual prototyping, physical synthesis, and full-chip hierarchical floor planning and placement. Cadence has received orders and delivered the new Encounter products to key SoC Encounter customers, including Agere Systems, CoSine Communications, and Toshiba America Electronic Components, Inc. (TAEC). These new products combine the virtual prototyping and hierarchical partitioning capabilities of SPCC's First Encounter with Cadence Physically Knowledgeable Synthesis (PKS) and Cadence CeltICsignal integrity technologies. First Encounter Ultra is designed to enable companies, such as high-end ASIC designers or customer-owned-tooling (COT) customers currently using other routing tools, to take their designs to timing qualified placement. SoC Encounter provides a complete hierarchical RTL-GDSII solution, which integrates First Encounter with the production-proven Cadence SiliconEnsemble®-PKS (SE-PKS). According to Sam Appleton, manager of Network Processing, CoSine Communications, "CoSine is designing four-million-gate-networking switches in 0.13 µm technology with an aggressive tapeout schedule. With its powerful hierarchical floor planner, Cadence SoC Encounter is the best solution we found that can tackle the design of these large chips. After evaluating the product in January, we decided to replace Avant! in our design flow with the Cadence SoC Encounter solution." "We chose First Encounter Ultra because of its capacity to handle very large, timing-critical IC designs," said Jon Fields, vice-president Design Platform Organization, Agere Systems. "Hierarchical design is mandatory for the scale of chips we're engaged on, and with this solution we're seeing impressive results on some extremely challenging designs." "To help us reduce design-cycle times of our ASIC customers' complex SoCs, we chose SoC Encounter as our hierarchical floor planning, placement, and analysis tool," said Jeff Berkman, senior vice president of engineering at TAEC. "We've found SoC Encounter to be an efficient solution for fast physical prototyping of large designs at small geometries." "With SoC Encounter, Cadence has delivered the industry's first hierarchical front-to-back solution for high-end IC implementation at 0.13 µm and below," said Ray Bingham, president and CEO of Cadence Design Systems. "We are also making critical advanced technology available in non-Cadence flows with First Encounter Ultra and our standalone CeltIC version." Hierarchical System-on-a-Chip Design Flow with Virtual Prototyping To enable the design of multimillion-gate ICs, SoC Encounter employs hierarchical design capabilities to partition chips into smaller blocks to be designed separately and later reassembled. SoC Encounter first reads in an RTL or gate-level netlist, and quickly constructs a full-chip "virtual prototype" that accurately represents the final chip, including timing, routing, die size, power, and signal integrity. With the physical virtual prototype feature, designers can quickly verify the design's physical feasibility and make any necessary changes to the logic. The prototype is then partitioned into hierarchical blocks, including pin assignments and timing budgets. Physical synthesis and detailed cell placement and routing are then performed at the block level. Finally, the entire design is assembled and any remaining signal integrity violations are detected and repaired. The integration of the prototyping, physical synthesis, and place-and-route technology provides better quality-of-results in clock frequency and area. The overall result is superior chip performance and a short physical design cycle. SuperChip Initiative The two new Encounter products represent the digital standard-cell component of the Cadence SuperChip initiative, designed to address the complete SoC integration challenge, including custom analog/mixed-signal electronics. SoC Encounter will incorporate advanced technology from the Cadence Integration Ensemble™ program within a few months, including support for the OpenAccess database and enhanced capabilities for integrating digital and analog circuits together. "Customer demand for the integrated technologies is a validation of our shared vision for design productivity," said Ping Chao, senior vice president and general manager of Silicon Perspective, a Cadence company. "Customers want a high-end design solution today, and we have it for them. We are seeing tremendous demand for these products, which shows how well our solution is fulfilling customers' hierarchical design requirements. Industry-leading design technologies coupled with the strength of the Cadence channel is a potent combination." Pricing and Availability Cadence SoC Encounter hierarchical IC implementation solution and First Encounter Ultra are available immediately for Sun Solaris and HP's HP-UX UNIX operating systems. One-year U.S. list prices start at $695,000 and $400,000, respectively. For information about upgrade paths for current customers or international pricing, please contact a local Cadence office.

Cadence embarked on its SuperChip Initiative several years ago with the goal of providing a comprehensive SoC design solution. The initiative is a co-development effort between Cadence, design companies, and select third parties. It was intended for the initiative to eventually encompass system design, IC design, PCB design, and embedded software development. Even though the initial focus was the digital-analog convergence, the two products announced are both for digital IC design. SoC Encounter, the first deliverable from the SuperChip Initiative, is a complete hierarchical IC design solution for up to 30 million gates at 0.13 µm, and goes from the construction of virtual prototypes through to the final GDSII tape. First Encounter Ultra, which is part of SoC Encounter, provides virtual prototyping, physical synthesis, and full-chip hierarchical floor planning and placement. The tools use technology that Cadence received when it acquired Silicon Perspective Corp. (SPC) in December, 2001. SPC's First Encounter product is an RTL virtual prototyping tool that included hierarchical floor planning, placement, and analysis.

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