TSMC Unveils Nexsys

The manufacturer says . . .

Murray Disman says . . .

TSMC Unveils Nexsys—The Technology for SoC 90 nm Technology Provides Industry-Leading System-on-a-Chip Integration and Performance SAN JOSE, Calif.--April 9, 2002--Taiwan Semiconductor Manufacturing Company (TSMC) unveiled Nexsys, the industry's next-generation technology for system-on-a-chip (SoC) semiconductor design and manufacturing. Nexsys design rules and SPICE models are available now to select customers. TSMC's Nexsys technology consists not only of process technology, but also a design environment and associated intellectual property (IP) and libraries. TSMC expects to begin first production of Nexsys-based 90 nm customer devices on 200 mm wafers in the third quarter of 2002, followed by 300 mm wafers beginning in the first quarter of 2003. "Nexsys is the industry's leading technology for the SoC era," said Dr. Kenneth Kin, senior vice president of worldwide marketing and sales for TSMC. "The first available Nexsys technology features 90 nm design rules, electrical and transistor characteristics and performance requirements, collaboratively defined with leading IDM and fabless companies worldwide. Nexsys provides designers with the density, performance, and time-to-market advantages necessary to empower innovative new products and applications that will redefine IC industry markets." On March 5 of this year, TSMC announced that it had successfully produced the foundry industry's first fully functional SRAM chips using 90 nm logic process technology. That milestone made TSMC the first foundry to deliver a functional 90 nm device, one year ahead of the SIA Roadmap. The device featured a 65 nm gate length, roughly 1,000 times thinner than a human hair. At this geometry, designers will be able to pack several million logic gates into a single chip, or populate the chip with multiple functional blocks, including mixed-signal blocks, embedded high-density memory, or embedded flash, to enable entire systems on a single chip. Process options include a general-purpose version (CLN90G), a high-speed version (CLN90HS), and a low-power version (CLN90LP) for computer, graphics, consumer, network, and wireless applications. A mixed-signal/RF CMOS version (CMN90) will also be provided for high-performance analog applications such as high-bandwidth networks. The high-speed versions of the process will support operating speeds in the multi-Gigahertz range. The Nexsys 90 nm process technology offers a triple-gate-oxide option for design versatility, and is expected to have a core voltage as low as 1.0 V, a gate length of 45 to 65 nm, and a gate delay as low as 7.9 ps for the high-speed process option. The process also features low-K dielectric of 2.9 or lower, and up to 10 layers of dual-damascene copper metalization. It is produced using the state-of-the-art scanning lithography systems with optical proximity correction (OPC) and phase-shift masks (PSM). Nexsys is supported by a broad portfolio of value-added libraries, intellectual property, electronic design automation (EDA) tools, and design services. A number of design centers worldwide have already received preliminary design rules, allowing these highly specialized design teams to support IDM and fabless semiconductor customers with process-specific engineering abilities.

TSMC is moving towards the 90 nm node at an alarming rate. The company has already fabricated a 4Mb SRAM using its Nexsys 90 nm process. It expects to begin first production of customer devices on 200 mm wafers in 3Q02, followed by 300 mm risk wafers in 1Q03. This schedule seems to be very optimistic since TSMC only recently qualified its 0.13 µm process and expects to deliver only 200K wafers from this process by the end of 2002. LSI Logic has also announced its 90 nm G90 ASIC product that, according to the company, is built on a process platform that they defined jointly with TSMC. LSI developed its 0.13 µm process with TSMC last year. LSI will begin working with selected customers during 2H02, after the design libraries have been released. Designs will initially be produced at TSMC, starting during 2Q03. ASIC designers are still struggling with 0.13 µm chips, and the 90 nm node will introduce additional difficulties as reliability concerns, signal integrity issues, and physical effects increase in importance. The design tools to handle these problems are not ready, and current timing closure and verification roadblocks will present increasingly greater impediments at the 90 nm node. TSMC has released Version 0.1 of the design rules and SPICE models to library and IP providers. The general release of this information is set for 3Q02. Process qualification and library release are also scheduled for 3Q02. TSMC started production at the 0.18 µm node in 1Q99. It progressed to 0.15 µm in 1Q00 and then to the 0.13 µm node in 1Q01. Each of these 15% feature-size-reduction steps took one year. It now plans on implementing a more than 30% decrease in 1.5 years. The company will be pushing sub-wavelength lithography to reach the 90 nm node. TSMC will be using the same 193 nm light sources it used for its 0.13 µm process for the new 90 nm process. This will increase the cost and complexity of the masks. Both optical-proximity correction and phase-shift mask techniques will have to be used for nearly all of the masks. This will push mask NRE costs up into the $1.5 to $3 million range. Deep pockets and a lot of fortitude will be required by the first companies migrating to this process node.

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