Get2Chip Introduces RTL Synthesis

The manufacturer says . . .

Murray Disman says . . .

Get2Chip Intros RTL Synthesis for 100M Gate Era RTL Compiler™—Best For Multi-Million Gate, High-Frequency Designs SAN JOSE, Calif.--April 15, 2002--Get2Chip Inc., the electronic design automation (EDA) supplier of multi-level, system-on-a-chip (SOC) synthesis, introduced its RTL Compiler (a.k.a. G2C-RC), a high-speed, high-capacity alternative for register transfer level (RTL) synthesis of multi-million gate integrated circuits (ICs). Optimized for designs larger than 1 million gates with aggressive clock speeds, G2C-RC provides a synthesis alternative for the SOC era, according to Get2Chip President and Chief Executive Officer (CEO) Bernd Braune. "G2C-RC is aimed at an under-served market needing consistent quality of results, super-fast run times, and confidence that new design tools will readily fit into existing flows and methodologies," adds Braune. "G2C-RC has seen more than 200 designs and has been built to be flow-compatible with the old technology designers have used for some time. With 100 nm silicon just around the corner, chip designers have been looking for this productivity boost at the front end." Michael Raam, Procket Networks' vice president of VLSI, has converted the company's production flows to Get2Chip's G2C-RC to design massive networking chips. "With Get2Chip's RTL Compiler in our COT flow, we achieved faster run time, an improvement in clock speed, correlation of timing with the back-end, some reduction in area, and compatibility with our existing EDA tools. Get2Chip is helping us to create superior products and bring them to market in record time in a highly competitive environment." To produce superior designs with less effort, Get2Chip's G2C-RC brings value-added features such as test insertion and power optimization to this class of products for the first time. New analytic technologies built into the software include a global-based optimization engine enabling linear behavior over design and library size; constraint-directed logic, power, and data-path optimization; and the industry's most efficient data representation. The total negative slack (TNS) optimization of G2C-RC increases timing margins to optimize more than a design's critical path, providing extra timing margin for near-timing-critical signals. To ensure ease of use, G2C-RC enjoys verified compatibility with a number of widely used EDA products, including simulators; verification, test, and analysis tools; and place-and-route software, including a specialized interface module to Avanti's Apollo. Additional technical information on G2C-RC, benchmark results vs. competitive synthesis offerings, and a list of compatible software can be found at www.get2chip.com. G2C-RC is now shipping. The base price is $100,000. Additional Quotes Garo Toomajanian, vice president and research analyst at RBC Capital Markets, offered his assessment of the Get2Chip market position. "The difference between Get2Chip and other synthesis alternatives is that Get2Chip is the only full-chip, system-level solution. With design closure issues in the back-end of the design flow now largely addressed, we believe the focus will shift upstream in the design flow to system-level issues. The opportunities to optimize designs are far greater and easier to implement at higher levels of abstraction, early in the design flow, than in back-end processes. Because of that, Get2Chip is well-positioned to give designers better results with less effort and in less time." "We have spent the last 12 months polishing the compatibility of G2C-RC," adds Dr. Hormoz Yaghutiel, Get2Chip's vice president of engineering. "When dealing with a 20 million-gate design, engineers cannot afford compatibility or interoperability issues. G2C-RC will upgrade existing design flows without interrupting the production process."

Get2Chip, started in 2000, already has recorded a sizable number of accomplishments. Its first product was the Volare (now called G2C-AC) architectural compiler. It released its G2C-RC RTL synthesis tool to selected customers last quarter. The company claims that some 300 designs have been implemented using its tools, and that 15 of its customers are now in production. G2C-RC is aimed at the more aggressive ASIC designs, competing directly with Synopsys' Design Compiler, as well as synthesis tools from other suppliers. The company makes some very impressive claims for the tool, which is based on what Get2Chip calls a global-focused mapping technique. According to the company, the new software architecture enables efficient data representations, and results in linear behavior over the design and library size. One difference claimed for the tool is that it first optimizes for timing, not area. One benefit of this architecture is that 2 million gate designs can be compiled on a 32-bit machine. Designs ranging from 70K to 2.6 million gates have already been implemented by customers. For example, a 2 million gate design was complied on a PC with 3 Gbytes of memory in 8 hours. This contrasts with Design Compiler, which can only effectively handle blocks of 100K to 200K gates. According to Get2Chip, G2C-RC has achieved an average of 15% better timing, 15% better area, 5 times better run times, and 10 times larger capacities in customer designs than competing tools. The company has benchmarks that show much better results for specific designs. The global-focused mapping algorithm is one of the reasons for the shorter run times. The algorithm includes a constraint-directed control mechanism for logic and data-path optimization. This, according to Get2Chip, results in fewer iterations, thereby shortening the run times.

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