Mentor Upgrades HDL Designer Series

The manufacturer says . . .

Murray Disman says . . .

Mentor Graphics HDL Designer Series 2002.1 Speeds Creation and Analysis of Complex Chip Designs WILSONVILLE, Ore.-- April 15, 2002--Mentor Graphics Corporation announced the 2002.1 release of its HDL Designer Series tool suite for design creation, analysis, and management. The tool suite offers productivity enhancements, including an improved interconnect table that enables rapid creation of high-quality, well-structured hardware description language (HDL) for any level of design complexity. HDL Designer Series speeds the creation and analysis of complex application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), and system-on-a-chip (SoC) designs, allowing teams to realize rapid time-to-market. "The complementary tools in the Mentor Graphics HDL Designer Series tool suite provide designers with a complete environment for HDL design, analysis, and management, regardless of their approach to HDL design," said Valerie Rachko, HDL Designer Series marketing director for Mentor Graphics. "Features such as Interface-Based Design have proven invaluable in simplifying the challenge of describing complex interconnect. Our new release strengthens documentation, visualization, debugging, and design management to facilitate team design." Interface-Based Design Methodology Simplifies Interconnect Description for Complex Designs Interface-Based Design (IBD) simplifies interconnect creation problems by displaying design interconnect structures in an easy-to-view, compact tabular format. This tabular editing environment allows designers to rapidly specify signal connections and generate the equivalent VHDL or Verilog structural description. The IBD description can also be viewed as a block diagram. HDL Designer Series 2002.1 provides significant new features to IBD, including capabilities to insert and delete nets and propagate changes across the hierarchy, re-level hierarchy by adding or removing levels, dynamically update between IBD and block-diagram views, expand or collapse rows and columns to customize view, and re-order rows and columns using drag-and-drop features. Improvements to Debug Detective The Debug Detective offering within HDL Designer Series enhances HDL simulation and improves productivity within a ModelSim® design flow. Debug Detective runs within ModelSim, using graphical and tabular diagrams of HDL source code to enhance design debug. New features and enhancements to Debug Detective include improved state-machine rendering recognition, configurable probe display, improved simulation control available from simulation toolbar and ModelSim menus, and extended probe change information and force control. Pricing and Availability HDL Designer Series 2002.1 is available now and starts at $2,000 US for a node-locked license. The tool suite is now available for Windows XP, Red Hat Linux 7.2, and HP-UX 11.11 platforms in addition to existing support for Windows 98, NT, and 2000, Solaris 7 and 8, HP-UX 11.00, and Red Hat Linux 6.2.

The primary improvements to HDL Designer Series are in its Interface-Based Design (IBD) and Debug Detective capabilities. HDL Designer Series is a suite of front-end HDL tools that is targeted at FPGA and ASIC designers. It contains HDL Pilot for design management; HDL Detective for design analysis and documentation; HDL Author for text and graphical editing; HDL Designer for point tool functionality; and Debug Detective for extending debug and design analysis capabilities to ModelSim simulation solutions. The price for the entire HDL Designer Series package is $24,000. Mentor Graphics is currently offering a free 30-day download of the tool suite.

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