Cadence Enhances Verification Cockpit

The manufacturer says . . .

Murray Disman says . . .

Cadence Delivers Verification Productivity Boost for Complex SOC Designs Through Commitment to Industry Standards Introduces Assertion-Based Verification Technology Based on Accellera Sugar Language; Adopts Open-Source SystemC for Design and Verification SAN JOSE, Calif.-- May 27, 2002--Cadence Design Systems, Inc., the world's leading supplier of electronic design products and services, enhanced its Verification Cockpit offering with new Assertion-Based Verification (ABV) technology supporting the Sugar 2.0 Accellera standard language. Cadence also announced SystemC open-language support for design and verification in its NC-Sim and open-source TestBuilder products. These moves demonstrate the company's commitment to improve design productivity through solutions based on industry standards and open interfaces. "Our ABV capability can help digital design engineers detect and eliminate errors earlier in the verification process," said Rahul Razdan, vice president and general manager of the Cadence System and Functional Verification Group. "SystemC support can efficiently bridge the gap between complex system design, and hardware/software implementation and verification." As part of the Verification Cockpit, ABV functionality includes Sugar 2.0 assertion language support, extended transaction-based analysis and debug, and new static-checking capabilities. This combination enables designers to capture specifications, requirements, and assumptions as assertions; verify them statically using static-check techniques, or dynamically using Cadence's industry-leading mixed-language simulator, NC-Sim; detect internal errors at or near their source; and record assertion activity as transactions in the same form as those already recorded from TestBuilder, Verilog, and VHDL test benches. The net result can be efficient, comprehensive transaction-based functional coverage analysis in a unified debug environment. Available this fall with ABV capability, Verification Cockpit configurations will vary according to customer needs. Pricing starts at $25,000. Native support of SystemC in the Cadence NC-Sim simulator will enable designers to mix SystemC, RTL, and analog mixed-signal descriptions. Designers also can view waveforms and hierarchy; control their C/C++, Verilog, and VHDL code; and easily debug in a powerful environment that offers mixed simulation of SystemC, Verilog, Verilog-A, VHDL, and VHDL-A open languages. Cadence supports TestBuilder verification extensions to SystemC 2.0. These enable designers and verification engineers to write reusable test benches quickly and concisely at a high level of abstraction in C/C++. "Cadence is working closely with the SystemC Verification Working Group, and has proposed inclusion of verification extensions in SystemC," said Eshel Haritan, engineering group director, Systems and Functional Verification Group at Cadence. "The ability to verify SystemC transaction-level models and reuse the test bench for RTL verification can speed time-to-market and eliminate the error-prone task of creating a new RTL test bench." SystemC simulation products will be available this fall, priced from $15,000.

Cadence is taking the high ground with its support of SystemC and Sugar. It has added Sugar-based assertion-based verification techniques to its Verification Cockpit software. Sugar from IBM is the language adopted as a standard by Accellera. Sugar is a long way from being a widely used verification language. It is competing with established languages that include Synopsys' OpenVera and Verisity's e. In addition, Synopsys is favoring Intel's ForSpec for assertion-based verification features. The company has added native support of SystemC to its NC-Sim simulator. It can now offer mixed simulation of SystemC, Verilog, Verilog-A, VHDL, and VHDL-A languages. In addition, Cadence intends to modify the TestBuilder library to be SystemC-compliant, and had proposed donating the class library to OSCI, the SystemC consortium. It is expected that Cadence will be announcing SystemC support for other products in the near future. Traditional ASIC designers do not seem at all inclined to accept SystemC or other C/C++ design approaches. They seem much more interested in Verilog extensions, and will probably be pleased with Accellera's System Verilog 3.0, which has a strong element of Co-Design's Superlog.

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